PSOC4 TCPWM overflow and compare output pulse too short to trigger PWM (UDB) block ?

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Anonymous
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Hi,

   

 

   

I have created a project where I am using the overflow (or cc) output of a TCPWM block to trigger a PWM (UDB) block via it's trigger input.

   

It is not however working.  I believe this is because the output pulse of the TCPWM block, as the datasheet states is only 2 SYSCLK cycles wide, which I have confirmed on an oscilloscope. 

   

The PWM block that requires triggering is running from a 100kHz clock and I am guessing that because a clock cycle for this block is much slower than the output pulse of the TCPWM block, that it does not see it.

   

To overcome this, I have added a PulseConverter block which converts the two SYSCLK cycle pulse into a 100kHz pulse and all works correctly.

   

Am I missing something ? and is the PulseConverter module the right way of overcoming the problem or is there another way that doesn't use up extra UDB blocks.

   

Any help gratefully appreciated.

   

Paul H

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6 Replies
ETRO_SSN583
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Have you configured the PWM trigger input as edge detect ?

   

 

   

Regards, Dana.

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Bob_Marlowe
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Datasheet says:

   

Note All inputs are double synchronized in the TCPWM. The synchronizer is run at HFCLK speed. After that (except PSoC 4100 BLE, PSoC 4200 BLE, PSoC 4100M, and PSoC 4200M, (Timer/Counter, PWM modes)), these signals are synchronized with the component clock.

   

This would mean that you should lengthen your start-signal until the component clock goes high.

   

 

   

Bob

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ETRO_SSN583
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I thought his issue is triggering a UDB PWM, not a TCPWM......that TCPWM is triggering the PWM ?

   

 

   

Regards, Dana.

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Anonymous
Not applicable

Thanks for the replies,

   

Dana - yes you are correct in that I am trying to trigger a UDB PWM.  I can't see any way to configure the UDB PWM block as anything other than edge triggered, the only trigger options are rising edge, falling edge or either edge (and I have tried all three)

   

Bob - Effectively that is what I have done with the PulseConverter block , I was wondering if there is any other way to do it that uses less resources.

   

Regards, Paul H

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ETRO_SSN583
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I would file a CASE on this. Since it is an edge triggered input you are dealing with something

   

here is really whacky.

   

 

   

You are correct.PWM can only be triggered on rise, fall, both edges.

   

 

   

To create a technical or issue case at Cypress -

   

 

   

www.cypress.com

   

“Support”

   

“Technical Support”

   

“Create a Case”

   

 

   

You have to be registered on Cypress web site first.

   

 

   

You could use verilog or discrete logic, like create a simple 3 bit SR, re-circulating a

   

2 clock high pulse in it. Or try a LUT for a solution.

   

 

   

The pulse stretcher you are using only uses 3 macrocells.

   

 

   

 

   

Regards, Dana.

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ETRO_SSN583
Level 9
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Consider posting your project so forum can look at the whole picture, or extract

   

s simple subset of the problem and post that.

   

 

   

“File”                                                             Creator

   

“Create Workspace Bundle”

   

 

   

 

   

Regards, Dana.

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