Generate clock signal with minimum delay and MHz freq (EZUSB FX2LP)

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Anonymous
Not applicable

Hi,

   

I am using FX2LP CY7C68013A USB controller and it is interfaced with FPGA for its output signal controlling application. Right now I am trying to generate clock signals on the port B of USB controller using Keil and its respective Firmware.

   

The code consist of configuring the CPUCS with 12MHz (0X00) and initializing the port B and its pin PB0, high and low with delay of 1NOP instruction. This is processed in a IF loop with counter of 255 (0 to FF). I observe the delay of 5.3us and the frequency is in range of KHz on PB0 (pin 44). The system clock given to controller is 24MHz.

   

How should I reduce this delay and generate clock in range of MHz with the above specs..??

   

Thanks.

   

 

   

Dhara

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Anonymous
Not applicable

Looks like the toggling is being done in a while loop which typically takes more instruction cycles.

   

Two methods to make this happen:

   

a) Use timer to generate interrupts and in the ISR, write a code to toggle a bit. This will provide a faster toggle time

   

b) Use GPIF to route toggle a pin. This toggling will be faster and will happen at the GPIF speed.

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