Compensating for Two's Compliment input for DFB Fitler

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sccac_1236541
Level 4
Level 4

Hi all,

   

 

   

I'm using the DFB filter block which takes in data as two's compliment values.  To compensate for this I have offset my original data so it is all positive.  I am transferring all the data via DMAs in and out of the filter to a buffer in SRAM.  I was wondering if there is any way other than manually using the cpu to de offset the data again so it is both positive and negative?

   

or rather and more preferred, a way to get the data into and out of the filter as negative values either by some trick with the filter or a way to convert the adc data into 2's compliment?

   

 I am going to analyzing the fft so I would rather not have a giant spike right at the beginning.

   

 

   

I was thinking of the possibility of using udbs (if even possible) or configuring a specialized data path, as I know that would probably work, but I have not created my own datapath yet and I know that can quickly get very hairy, and I don't have much of an idea where I would start.  But I'm more than willing to learn if that's the only option.

   

 

   

If you frequent these forums, you probably remember at least one of my previous questions since they are all similar to each other.  I AM making substantial progress on my project, and I do spend quite a bit of time reading through the ANs and troubleshooting my code. 

   

 

   

All your help is/has been greatly appreciated.

   

 

   

-scarlson

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6 Replies
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

scarlson,

   

do you want to offset input or output of DFB? The output will be always centered around 0 no matter whether input is positive or centered around 0.

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ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

You could use A/D EOC to trigger ISR that does the offset and place the

   

sample in memory, then trigger the DMA to move the sample. Or delay

   

EOC to DMA trigger, to allow ISR time to do the correction.

   

 

   

Regards, Dana.

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ETRO_SSN583
Level 9
Level 9
250 likes received 100 sign-ins 5 likes given

Or use filter ISR output to use the following ISR -

   

 

   

CY_ISR(filterVDAC)
{
    /* Convert the 2's complement value to an unsigned 8-bit value
     * The VDAC expects an unsigned 8-bit value as input.
     */
    VDAC8_SetValue(Filter_Read8(Filter_CHANNEL_A) + 128u);
}

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sccac_1236541
Level 4
Level 4

@ odissey1

I would like for both if possible, it would make my life easier in the long run, but I could live with just the output being centered around 0.  I do not think it is centered around zero by default.  When I look at the output of the filter it is definitely offset like the input.  Is there something I may be missing?

   

 

   

@ dana

   

I like your second idea, although if I'm thinking right, an unsigned value would still be offset.  My functions take in signed values so a it wouldn't work anyway (at least I don't think so). 

   

I guess I could flip the msb and I think that would give me a signed (although inverted) input?

   

 

   

 

   

Thanks guys

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted
        scarlson, something is wrong, the output of DFB always had DC offset removed by default. Long ago I asked Tech Support to add (optional) DC offset for direct DMA transfer to DAC, but I would be surprized if they hey did it without a notice.   
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sccac_1236541
Level 4
Level 4

Thats surely not what I am seeing.  Can anyone else confirm this? I am using creator 3.2.  I suppose you could easily just filter out the DC offset.. but thats not exactly what I'm looking for and I would obviously lose lots of other valuable data close to 0 as a result.

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