I've almost got my ISR's functioning how they should. The final part of this I can't figure out is why one of my timers is failing to capture on the first rising edge of a sampled signal. The relevant code is listed below, and I can upload parts of the project if that would help.
This is essentially a spinner RPM meter using offset reed switches that allows both spin direction and spin magnitude to be determined.
The inputs to both Timers are MUX'd to allow the entire system to sample input channel 1 first, followed by input channel 2, followed by input channel 1 again, and so on. One timer measures the period of the input channel being sampled, while the second measures the time elapsed between when the input channel being sampled drops low to when the next channel starts being sampled. Thus, the first timer gives frequency magnitude, while the second timer allows the direction of the spinner to be determined by comparing time between reed switch trips.
This Timer input is MUX'd, and toggled (from input 1 to input 2) immediately after a falling edge on the current channel is detected and the timer consequently triggered. Then, on the first rising edge detected input 2, the timer should take a capture. This happens successfully on every other sample. Whenever the system is sampling input channel 2, the timer fails to capture on the first rising edge; it only successfully performs a capture on the second rising edge. I've included a screenshot detailing this. The A1 and A2 markers show where the Timer is triggered, and where it should capture. The orange channel shows that the capture actually occurs on the second rising edge after the Timer is triggered.
What could possibly be causing this? The only thing I disable after the Time Elapsed Timer is triggered is the Trigger ISR itself to prevent a premature trigger before the period sampling is complete. When the MUX is toggled, the timer is also disabled then re-enabled to prevent the MUX line from triggering/capturing due to a MUX switching artifact.
The Code;
if( TETrigger_Flag ) {
DigDebug2_Write(1);
TETrigger_Flag = 0;
CyGlobalIntDisable;
TETriggerISR_Stop(); // Disable ISR
TElapsed_Timer_Stop(); // Disable Timer
if(RS_Sample == 1) // RS2
TElapsedMUX_Write(0); // RS1
else
TElapsedMUX_Write(1); // RS2
TElapsed_Timer_Start();// Enable Timer
TECaptureISR_ClearPending();
TECaptureISR_StartEx(TECaptureISR);
CyGlobalIntEnable;
DigDebug2_Write(0);
}
if( TECapture_Flag ) {
DigDebug3_Write(1);
TECapture_Flag = 0;
CyGlobalIntDisable;
switch(RS_Sample) {
case 0:
{
uint32 RS1_RawTElapsed = TElapsed_Timer_ReadCapture();
Sen_Data.RS1.dTimeElapsed = Timer_Period - RS1_RawTElapsed;
break;
}
case 1:
{
uint32 RS2_RawTElapsed = TElapsed_Timer_ReadCapture();
Sen_Data.RS2.dTimeElapsed = Timer_Period - RS2_RawTElapsed;
break;
}
default:
break;
}
TElapsed_Timer_Stop(); // Disable Timer
TECaptureISR_Stop();
TElapsedTimer_Reset_Write(1);
TElapsedTimer_Reset_Write(0);
TElapsed_Timer_Start();
CyGlobalIntEnable;
DigDebug3_Write(0);
}
if( PeriodTrigger_Flag ) {
DigDebug4_Write(1);
PeriodTrigger_Flag = 0;
CyGlobalIntDisable;
PeriodTriggerISR_Stop();// Disable ISR
TETriggerISR_ClearPending();
TETriggerISR_StartEx(TETRIGGER_ISR); // Enable ISR
TElapsed_Timer_EnableTrigger(); // Enable Timer
CyGlobalIntEnable;
DigDebug4_Write(0);
}
if( PeriodCapture_Flag ) {
DigDebug5_Write(1);
PeriodCapture_Flag = 0;
CyGlobalIntDisable;
switch(RS_Sample) {
case 0:
{
uint32 RS1_RawPeriod = Period_Timer_ReadCapture();
Sen_Data.RS1.dPeriod = Timer_Period - RS1_RawPeriod;
break;
}
case 1:
{
uint32 RS2_RawPeriod = Period_Timer_ReadCapture();
Sen_Data.RS2.dPeriod = Timer_Period - RS2_RawPeriod;
break;
}
default:
break;
}
Period_Timer_Stop(); // Disable Timer
if(RS_Sample == 0) // RS1
RS_Sample = 1; // RS2
else
RS_Sample = 0; // RS1
PeriodMUX_Write((unsigned short)RS_Sample);
PeriodTimer_Reset_Write(1);
PeriodTimer_Reset_Write(0);
Period_Timer_Enable(); // Enable Timer
Period_Timer_EnableTrigger();
PeriodTriggerISR_ClearPending();
PeriodTriggerISR_StartEx(PERTRIGGER_ISR); // Enable ISR
CyGlobalIntEnable;
DigDebug5_Write(0);
}
If further information is required, I will do my best to respond in a timely manner.
