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Hello,
I'm using the CYBLE-022001 module and I would like to use the LFCLK as clock of a counter block. But I have always the same error: M0139: Invalid connection for clock input ... The component requires a clock from the clock block.
What is the clock block? Is there a way to use the LFCLK in counter component?
Thanks in advance,
Gemotech
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Only the WDT wilkl run in deep sleep, see attached table -
http://www.cypress.com/?rID=110007 AN92584 - Designing for Low Power and Estimating Battery Life for BLE Applications
Regards, Dana.
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Only HFCLK can be used as clock input for the peripherals.
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Thanks for your responses.
I found a solution to use LFCLK with the counter block via an external connection: I can put LFCLK as output and define a Design-Wide Clock from an input pin (connected to the other output pin). I have to test now if the Timer counter peripheral is working in deepsleep mode.
Otherwise, is there any other solution to capture a frequency with WDT?
Best regards, Gemotech
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UDB Blocks in retention in deep sleep -
http://www.cypress.com/?rID=110007 AN92584 - Designing for Low Power and Estimating Battery Life for BLE Applications
http://www.cypress.com/documentation/application-notes/an86233-psoc-4-low-power-modes-and-power-redu... AN86233 - PSoC® 4 Low-Power Modes and Power Reduction Techniques
See attached Table.
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Thanks Dana, but I'm using the CYBLE-022001 module and it doesn't have UDB blocks. So I'm using the basic timer counter block.
I have to test if this timer counter is working in deep sleep. I will let you know ...
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My apologies for not observing the module you are using.
I did look at power supply current in deep sleep, it looks too low
to have a TCPWM counter running, although it does not specifically
state anywhere what is running other than the WCO.
Consider filing a CASE.
To create a technical or issue case at Cypress -
www.cypress.com
“Design Support”
“Create a Support Case”
You have to be registered on Cypress web site first.
Regards, Dana.
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Dear Dana,
I tried the solution with an external Pin but unfortunately it doesn't work...
I need to measure low frequencies whose starting to 1Hz to around 200Hz. If I cannot use the LFCLK clock it is really a problem because my system will always in sleep mode and the consummation is too high. How it possible to connect LFCLK clock to a standard counter not UDB counter?
Thank you for your help,
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Again, only the WDT runs with LFCLK in deep sleep, what hinders you to use that?
Bob
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How often, at what rate, do you have to measure the frequency ?
Regards, Dana.
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@BOB:
OK, I know that the HFCLK doesn't work in deep sleep mode, but if it isn't possible to use a counter in deep sleep mode that is a big problem for the Psoc4... it is why I would like to find a solution to use LFCLK
@Dana:
I need to measure the frequency every second
Regards, Greg
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Greg, the WDT is realized as a counter running with LFCLK. Are you thinking to count an exterrnal signal in deep sleep? As long as frequency is higher than 1/startup time that will not work at all.
Bob
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I would like to measure a square frequency from an external signal in deep sleep mode from 0Hz to 200Hz. With the timer, I can use the capture mode in rising/falling edge and it is automatic, but how can I use the WDT to do this? Is there a similar function with the WDT?
Greg
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No, there is no facility as capture on WDT timer. But you can wakeup from deep sleep with rising edge of your frequency, read out the WDT counter and calculate the frequency. Then go to deep sleep again.
Bob
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Since you have to measure up to 200 Hz, power wise, wake up once a second,
and measure your frequency. Do not use freqin as the wakeup signal, as that
would cause much more power consumption at the high freqin limit.
Since you are measuring a square wave just measure high time, and
double that, thats your period, and shutdown. Because of long gate
times at the other extreme, 1 Hz, how accurately do you wish to
measure this ? You might want to use reciprocal counter freq
measurement to do the measurement. Reciprocal counter uses the
freqin as the gate (just the opposite of "normal" counter) and a higher
frequency (which sets resolution) as the clock in. So at 1 Hz freqin,
and using 1 Khz as reciprocal gate, you would measure 500 clocks
for the high time, 10 Hz would be 50 clocks, 100 Hz would be 5
clocks. So at 100 Hz your resolution would yield 1 clock in 5 error,
not counting +/1 1 clock counting error, or 20% accuracy. Raise the
reciprocal gate freq if you want more accuracy.
See attached for discussion of reciprocal counters.
Regards, Dana.
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Finally, I decided to use the WDT with LFCLK for low frequency, under 5 Hz , with a good accuracy for my application. If the frequency is above 5Hz, I use the counter with the HFCLK and the result is good.
With this method, I can decrease the global system consumption
Thanks for your help and advise.
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There is a way to increase the precision of the LFCLK by comparing it to the HFCLK and calculate an adjustment. The PSoC4-M kit has got a deep-sleep example where that is done. Download the Kit files and search for Deep Sleep
Bob