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Hi all,
I´m doing a very easy project with the 5LP kit and Creator 3.3, where i need to generate a PWM signal with 10ms period (and a tiny positive duty cycle), no problems if i compile the project in Debug Mode, i see what i expect on the logic analyzer, but if i change the mode to Release i get a 1.28 ms period.
Does Release mode do any optimizations on the code? I'm only starting the PWM Component on the main loop, nothing else. I have not access to an oscilloscope, i guess the logic analyzer is enough for this. Hope this is not a n00b error.
Attached two screenshots and the easy project.
Thanks in advance
Carlos
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I am quite sure that your issue comes from a bad trigger for your logic analyzer. Try to select a port where no LED is connected to.
Bob
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I would never thought that was a issue. So the signal is the same on the release and debug mode but the Logic Analyzer
misinterprets it and throw just garbage? An oscilloscope would have this issue?
I place the signal to P1[7] and all is perfect now, thanks for solve it Bob.
Carlos
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It isa question of trigger setting which is more variable on an oscilloscope. But I think a logic analyzer is quite more versatile because of (usually) more channels and capabilities to convert a signal to a communication data stream.
Bob
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Indeed, will take this on account next time i try test digital signals with the LA.
One question, i´m testing ASM code, is any way to count the cycles every instruction takes on the debug session? I can't find it, i was thinking on take the cpu clock to a pin and toggle another pin to count the cycles, any idea?
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We had some similar discussions here already. The PSoC5 core CPU is quite modern, but the clock frequency is not very high. But the internal hardware inside the PSoC is unmatched. Having a PWM running at more than 10MHz, ADCs up to 1MHz conversion rate and internal signal processing with more than 60MHz... what more do you need!
When you are a bit more specific (could be even a byte more) what you want to perform, we could help you to find a solution.
Bob
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The pwm project is generate a 'spike' to feed a piezoelectric transducer (it's the first stage of a school project), then i will have to read the analog response of the receiver transducer with the adc (about 30 Msps) and send it via usb to the pc. But i'm starting, will post more questions in the next weeks for sure haha, that's why in the screenshots on the Saleae GUI is a file named DMA_, i was testing the DMA examples of the "Getting started with DMA" appnote.
About the asm, i'm trying nothing fancy, just learn asm, i was able to create a function on asm, and call it on the main file (at least it seems it's working), but would like to know how much clock cycles it takes, i must search on the Technical Reference Manual of the core i guess.
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30Msps seems a bit high. And? Did your assembly function beat C-Language optimized for speed?
Bob
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That's what i can't be able to measure, it's a microseconds delay function, as i say nothing fancy.
I remember Dana tell another user that in the generated files after compilation there is a file that give you the time that every function takes to execute, but i can't remember now what file it was 😕
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Just realize that it is 30 Msps and not 30 ksps (as i thought :/) , seems like PSoC internal faster ADCs is only capable of 1 Msps.
Now i'm trying to get 2 PWM signals with 40 Hz freq., it's fast with the PWM Component, but is it possible to get both signals out of phase (one signal per component)?
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You may start two (or more) PWMs with a control register to have them in a defined phase. When the offset has to be varied, I would make use of interrupts, since those get handled easily within a millisecond which would not matter much at 40Hz.
Bob
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Hi Bob,
Yes, i end up controlling the enable input of the PWMs with a Control Register, i enable the first PWM plus a delay between enabling the second PWM, seems like it's working as expected.
I think i will have not to change the offset, only the duty cycles. will ask if more questions arrive
Thanks again
Carlos