Hello.
I have experienced problems since updating from Creator 3.1 with a PSoC 5 design implementing a custom SPI bus to run at high speeds for interfacing an SD card. It uses a component built in the UDB editor (as my verilog skills are non existent). I previously posted a query at
http://china.cypress.com/comment/283971
I was advised to open a MyCase, but never got around to it due to other things getting in the way. Now my job requires me to return to developing my system, I have investigated the problem again to get back up to speed with my source code. Before getting back to posting a MyCase, I thought I would query the community - there is only one difference between generated verilog between Creator 3.1 and later versions:
Creator 3.1:
8'hFF, 8'h00, /* CFG9 */
8'hFF, 8'hFF, /* CFG11-10 */
`SC_CMPB_A1_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH, `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_ROUTE, `SC_SI_A_ROUTE,
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0, `SC_SR_SRC_REG, `SC_FIFO1_ALU, `SC_FIFO0_BUS, `SC_MSB_ENBL, `SC_MSB_BIT7, `SC_MSB_NOCHN, `SC_FB_NOCHN, `SC_CMP1_NOCHN, `SC_CMP0_NOCHN, /* CFG15-14 */
3'b000, `SC_FIFO_SYNC_NONE, 2'b000, `SC_FIFO1_DYN_OF, `SC_FIFO0_DYN_OF, `SC_FIFO_CLK1_POS, `SC_FIFO_CLK0_POS, `SC_FIFO_CLK__DP, `SC_FIFO_CAP_AX, `SC_FIFO__EDGE, `SC_FIFO__SYNC, `SC_EXTCRC_DSBL, `SC_WRK16CAT_DSBL /* CFG17-16 */
Creator 3.3:
8'hFF, 8'h00, /* CFG9 */
8'hFF, 8'hFF, /* CFG11-10 */
`SC_CMPB_A1_D1, `SC_CMPA_A0_D1, `SC_CI_B_ARITH, `SC_CI_A_ARITH, `SC_C1_MASK_DSBL, `SC_C0_MASK_DSBL, `SC_A_MASK_DSBL, `SC_DEF_SI_0, `SC_SI_B_ROUTE, `SC_SI_A_ROUTE, /* CFG13-12 */
`SC_A0_SRC_ACC, `SC_SHIFT_SL, 1'b0, `SC_SR_SRC_REG, `SC_FIFO1__A0, `SC_FIFO0_BUS, `SC_MSB_ENBL, `SC_MSB_BIT7, `SC_MSB_NOCHN, `SC_FB_NOCHN, `SC_CMP1_NOCHN, `SC_CMP0_NOCHN, /* CFG15-14 */
3'b000, `SC_FIFO_SYNC_NONE, 2'b000, `SC_FIFO1_DYN_OF, `SC_FIFO0_DYN_OF, `SC_FIFO_CLK1_POS, `SC_FIFO_CLK0_POS, `SC_FIFO_CLK__DP, `SC_FIFO_CAP_AX, `SC_FIFO__EDGE, `SC_FIFO__SYNC, `SC_EXTCRC_DSBL, `SC_WRK16CAT_DSBL /* CFG17-16 */
Can't tell if the above will post in a legible fashion.. However Creator 3.1 uses SC_FIFO1_ALU in the datapath configuration section, whereas Creator 3.3 uses SC_FIFO1__A0 in the corresponding location.
I have found that I can override the verilog generated by Creator 3.3 by creating a verilog file as a component item in the UDB component in my project and pasting in the Creator 3.1 version of the verilog. This avoids the problem (so long as I don't need to edit the component design), but leaves me wondering if I'm relying on a bug in Creator 3.1 and should change my design, or if there is a bug in later versions of Creator.
