Anonymous
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Dec 21, 2015
02:37 AM
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Dec 21, 2015
02:37 AM
I have a design where I want to read some data from the Fx3 PPORT to an FPGA using the slave interface. I am using a 8-bit bus. I am finding that the data takes 3 clocks from setting the SLRD signal low. I read in the datasheet that it is supposed to be 2. So I am a bit confused why I am getting 3.
Thanks
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Anonymous
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Dec 23, 2015
03:19 AM
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Dec 23, 2015
03:19 AM
Hi,
The extra clock cycle is when you see it from FPGA's perspective. FX3 takes only 2 clock cycles to latch the data, the one more clock cycle is required by FPGA to sample it.
Regards,
- Madhu Sudhan