How to change the frequency of the GPIF clock?

[waxi_1305956]

Hi,i am using the GPIF connect to a FPGA.I use the GPIF as the master and synchronous mode.I want to know how to set the frequency of the GPIF port and how to set that it will be the fast 100MHZ?

[Anonymous · Accepted solution]

Hi,

   

In the firmware the CyU3PPibInit  API is used to initialize the PIB Block and also set the GPIF Clock.

   

For setting it as 100 Mhz, Please use the following snippet:

   

    CyU3PPibClock_t              pibclock;

       

   /* Initialize the P-port. */
    pibclock.clkDiv      = 4;
    pibclock.clkSrc      = CY_U3P_SYS_CLK;
    pibclock.isDllEnable = CyFalse;
    pibclock.isHalfDiv   = CyFalse;

   

    apiRetStatus = CyU3PPibInit (CyTrue, &pibclock);
    if (apiRetStatus != CY_U3P_SUCCESS)
    {
        CyU3PDebugPrint (4, "PIB Function Failed to Start, Error Code = %d\n", apiRetStatus);
        CyFxAppErrorHandler (apiRetStatus);
    }

   

In this, the clkDiv is the divisor on the SYS_CLK for getting the GPIF Clock. The SYS_CLK may be 384 MHz or 403.2 MHz depending upon whether the 'setSysClk400' field in CyU3PDeviceInit is set as CyFalse or CyTrue respectively. So far getting 100 Mhz, you need to set this as CyTrue, so that the SYS_CLK is 403.2 MHz and GPIF Clock is 100.8 Mhz.

   

Regards,

   

-Madhu Sudhan