DMA won't execute transfers when set up properly

[sccac_1236541]

I've been using DMA in several projects lately, all working fine after some trial and error, but I'm using a slightly different project and now it won't work.

       

my DMA reads in the different values from the SPIM component's rx ptr (I have done this several times) but instead of putting them into one array, it separates each 32 bits into 3 different arrays (every 32 bits goes to 1 of the 3 arrays).  It does this by using some verilog to multiplex through which DMA the SPIM_rx_INT triggers.  

   

I have verified the verilog component is working properly and with zero delay, but for some reason when I have it inside my project the DMAs do not seem to transfer anything, and the TD done output is never set.

       

I previously had a similar setup where I had the

   

SPIM>DMA(3 TDs each with a 32bit value) >verilog to sequence DMAs creating the arrays>3 DMAs to create 32-bit arrays,

       

and this setup worked just fine, but I wanted to switch my setup around to free up some DMAs and stop wasting time reading/writing from sram.  

       

What I want to have is,

   

SPIM>verilog to sequence DMAs creating arrays>3 DMAs to create 32-bit arrays.

   

but the DMAs are not transferring for some reason

       

I am posting my project here, if someone feels generous I would appreciate it if they could give their input, I am out of ideas for where to look.

[Bob_Marlowe]

As I understand this, you need four DMA channels, one to fill an array of three 32-bit numbers and three to pick a number and put it into the appropriate array. Because a PSoC5 has got 24 DMA channels you are not wasting many resources when using 4 channels instead of 2. No verilog component needed. You probably know already this document which covers that topic.

       

Bob

[sccac_1236541]

I must either be wrong or I think I'm doing something slightly different that makes the examples in the datasheet not apply.  I think the main difference is how I receive the values.  I get them 4 bytes at a time, to create a 32-bit word, which I want to send to an array of size n words.  the problem is I have 3 words coming in over the spi, in sequence (ie word a, word b, word c, word a, ...), and I want to create array a, array b, and array c all of some length n.  I don't think this is done in any of the examples.

       

I came p with a verilog component to solve this.

       

again I could be understanding it all wrong... 

[Bob_Marlowe]

What is wrong with my first suggestion?

       

Bob

[sccac_1236541]

I think youre suggestion would generally work,

   

I agree I could use two DMAs, one with 3 TDs that creates the 32-bit words, acting as a staging point for the values, and then trigger a term out signal at the end of the 3rd to start a second DMA with 3 TDs that populates arrays a,b,c from words created via the first DMA.  

       

The problem is I am using the second DMA to store the data on external sram and because its an 8-bit I must set the burst count to 1 but I cannot increase the src addr either since my length is very large and I am increasing the destination.  I would also like to not have to wait until all 3 TDs of the first DMA are finished before populating arrays a and b since theres a notable amount of delay between when I receive my values over spi.

       

Does this change what you were thinking or am i still missing something?

[Bob_Marlowe]

Yes, the 8-bit sram interface complicates the situation.

       

Bob