- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello,
I'm using the ShiftReg component but not as expected
there are some glitch on the output I do not understand..
Can somebody help me?
Regards
<code>
int main()
{
uint32 Current_Value = 0x884444;ShiftReg_1_Start();
ShiftReg_1_WriteRegValue((Current_Value<<2) | 0x2000001);...
</code>
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
If you could tell what the signals in your screenshots actually mean, and what you expect them to look like, maybe we can have a guess.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
WriteRegValue() should be used only when the shift register is stopped and I cannot see any reloading.
You do not write into the FIFO from where it will be loaded with a "load" signal.
I cannot see any dependency from the rising edge of clock to the register output in your LA pics.
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hello
I used the code example from the Shift Register Component Data Sheet 1.50, page 13 to initially load the shift register with a 26 bit value (0x3108889)
Then when I press the push button I allow the clock to shit the value : after 26 pulse I stop the pulse train.
The aim is to send a predefined train of 26 pulses.
I do not understand why there is no correlation between P1_ (clock) and P1_4 (shift_out)
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I do not understand why there is no correlation between P1_ (clock) and P1_4 (shift_out)
Neither I do, but I would try to concentrate on that. Only dependency seems to be at the time of the glitch.
Because I trust such a simple device like a shift register I would suspect other sources for the issue.
Capacities on the output pins. What kind of board are you using? Cypress kit?? Which one???
- Logic analyzer connection.
- Pushbutton spikes
- Others...
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
I suggested some corrections, did you implement them? attach latest project archive, please.
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Hi Bob
I found my problem, The malfunctioning output were connected to another board with conflicting output. I disconnect them and now everything is OK, Sorry for not checking that before.....
Thanks for your help
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
You are always welcome!
A tip that easily pays: Get a CY8CKIT-043 PSoC4-M Prototyping Kit. No bootloader required, debugging capabilities, DMA and more sram for few money.
Bob
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Looks fine , I will buy one....
Best Regards
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
The most important thing is that the "q" output of the "TFF" component cannot be used for a clock input for other components directly in PSoC 4.
In this schematic, you are expecting the "TFF" component divide the 1MHz clock to generate a 500kHz clock. Actually a clock can be generated from a "TFF" output in PSoC 3 and 5LP. But clocks can be generated only from a HFCLK and clock dividers in PSoC 4. In other words, TFF cannot be used to generate a clock.
Following is a synthesis detail of a bit of Shift Register from the RPT file generated by PSoC Creator.
LIST-1
[McSlotId=2]: MacroCell: Name=Net_859_3, Mode=(T-Register) @ [UDB=(0,0)][LB=0][MC=2]
Total # of inputs : 6
Total # of product terms : 2
List of special equations:
Clock = (Net_962_digital) => Global
Clock Enable: PosEdge(Net_928)
Main Equation : 2 pterms
(
!Net_852 * Net_519 * Net_859_2 * Net_859_1 * Net_859_0
+ Net_852 * Net_859_3
);
Output = Net_859_3 (fanout=4)
Properties :
{
}
In line 05, it is described that a global signal Net_962_digital is used as the clock input.
LIST-2
<CYPRESSTAG name="Global Clock Selection" icon="FILE_RPT_TECHM">
Digital Clock 0: Automatic-assigning clock 'Clock_1'. Fanout=5, Signal=Net_962_digital
Fixed Function Clock 2: Automatic-assigning clock 'UART_1_SCBCLK'. Signal=\UART_1:Net_847_ff2\
The Net_962_digital is the output of the clock "Clock_1" The "TFF" output is not connected to the clock input.
Instead of connecting the 500kHz clock, it is described in line 06 of the "LIST-1" that a clock enable input is used to detect the positive edge of the Net_928 signal. There is a one clock delay to detect the Positive Edge, so the timing of the Shift Register may be different from other logics.
Please consider to use a single clock domain.
Regards,
Noriaki