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In learning to use datapaths, I created a simple 8 bit counter. It works fine if I use a synchronized input. If I switch to an asynchronous input, it says I need the UDB Clock Enable. It works fine if I put one of these on the schematic and wire it up.
However, I really want to have the UDB Clock Enable as part of the verilog code for the 8-bit counter. If I instantiate:
cy_psoc3_udb_clock_enable_v1_0 #(.sync_mode(`FALSE))
udbclkenable(
.clock_in (CountIN),
.enable (1'b1),
.clock_out (A_CountIN)
Where CountIN is the input clock, and A_CountIN is the clock for the datapath, I get errors on build that say fixed location constraints cannot be satisfied.
My verilog is very rusty.... but I feel I am missing something.
Thanks for any advise.
Mark
Solved! Go to Solution.
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Mark,
This is not right forum. Please move it to PSoC5 programming or elsewhere. When re-posting, attach a project workspace bundle (use
Creator->File->Create Workspace Bundle (minimal)).
I believe to have datapath working correctly, you need to instantiate a clock sync inside the Verilog code. That's why your external sync worked. You can find example of clock sync code inside almost any Cypress component (look for *.v).
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Mark,
This is not right forum. Please move it to PSoC5 programming or elsewhere. When re-posting, attach a project workspace bundle (use
Creator->File->Create Workspace Bundle (minimal)).
I believe to have datapath working correctly, you need to instantiate a clock sync inside the Verilog code. That's why your external sync worked. You can find example of clock sync code inside almost any Cypress component (look for *.v).
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Ok, thanks. It seemed that since this was a component forum that it made sense here, but PSoC5 programming is just as good.
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I resolved it. I had verilog code which was set at the positive edge of the incoming asynchronous clock signal. However, I placed the clock sync after that code. By moving the clock sync before the positive edge checking code, and then made certain that I changed all remaining clock's to the new synchronized one, all is fine.