what is the role of the Vref in PGA module

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Anonymous
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Hi,dear

   

    i have some questions about the PGA module as follow:

   

1.what is the role of the Vref in PGA module?

   

2.when the gain was setted 50,but the output voltage (Vout )is less than 50 times of the input voltage(Vin=0.02sinwt+1.024,f=2k Hz).

   

result:Vpp of  Vout is 763mv,wave of output voltage shown in the attachment .

   

Looking forward to your reply.Thank you.

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HeLi_263931
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Have a look at the data sheet of the component.

   

Vref acts as virtual ground: Vout=Vref+(Vref-Vin)*gain

   

When the difference between Vref and your input signal is too large, then the PGA will go into saturation - its output range is just between Vcc and Vdda.

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HeLi_263931
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Have a look at the data sheet of the component.

   

Vref acts as virtual ground: Vout=Vref+(Vref-Vin)*gain

   

When the difference between Vref and your input signal is too large, then the PGA will go into saturation - its output range is just between Vcc and Vdda.

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Anonymous
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its output range is just between Vcc and Vdda?

   

is  not between vss and vdda? my psoc system's vdda is 5V.

   

my idea about above :Vout=Vref+(Vin-Vref)*gain=1.024+(0.02sinwt+1.024-1.024)*50=sinwt+1.024,Vpp between 0.024 and 2.024(Vpp=0,024~2.024)

   

but the Vpp of output is only equal to 412 mV.

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HeLi_263931
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Sorry, I meant Vss.

   

Vpp should not a range, but a maximum value (its 'peak-to-peak'). So lets calculate: a voltage of 24mV (l assume its 25mV above Vref) would give a output of 24*50=1200mV. So if its 24mV _below_ Vref you are driving the output to ground already.

   

Can you show a scope shot of your input and output signals? Preferably with DC coupling (so the DC offset can be seen), and Vref from the PSoC as reference? (Just route it to an output pin). The image you added is not helpful without seeing the amplitude of the input signal, and how its related to Vref (and btw. it shows a Vpp of 750mV, not 412mV).

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Anonymous
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Sorry, Are you sure "I assume its 25 mV above Vref",but not "I assume its 24 mV above Vref" ?

   

1.My idea:Vout=Vref+(Vin-Vref)*Gain=1.024+[(0.02sinwt+1.024)-1.024]*50=1.024+sinwt, so the Vpp of  Vout should be 2000 mV, but showed 376 mV on the screen of scope. Does it mean the Gain=376/40=10?(But Gain was setted by 50),Why?

   

Additionally:

   

1.Vref  is  1.027 measurement by multimeter from pin_3 in the circuit of PGA.

   

2.The input signal , output signal and circuit of PGA were shown in attachment,pleases find what you want.

   

 

   

 

   

 

   

   

   

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Maybe I'm missing something, but the only waveform I see is Vout, in your first post. And there its showing a Vpp of 756mV, which doesn't fit your explanations. Thats why I was asking. (And your schematic doesn't show a pin_3, but I assume you changed it to route Vref to a pin).

   

So when "0.02*sin(wt)" is a sine wave with 40mV Vpp, with 1.027V DC offset, this gives a an input signal from 1.007 V up to 1.047 V. You should be able to verify that. This signal should end up, when the gain is 50, as a sine wave with a Vpp of 2V. So it should range from 0.027V up to 2.027V. YOu cannot drive the OpAmp closer than 50mv to ground, so there is a limit there.

   

Can you test your circuit with a controlled DC input? You need a voltage source that can be controlled very precise, since you need to test in just a 40mV range.

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Anonymous
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sorry ,i dont know how upload a image when give a comment yesterday.

   

Sorry, Are you sure "I assume its 25 mV above Vref",but not "I assume its 24 mV above Vref" ?

   

1.My idea:Vout=Vref+(Vin-Vref)*Gain=1.024+[(0.02sinwt+1.024)-1.024]*50=1.024+sinwt, so the Vpp of Vout should be 2000 mV, but showed 376 mV on the screen of scope. Does it mean the Gain=376/40=10?(But Gain was setted by 50),Why?

   

Additionally:

   

1.Vref is 1.027 measurement by multimeter from pin_3 in the circuit of PGA.

   

2.The input signal , output signal and circuit of PGA were shown in attachment,pleases find what you want.

   

3.I cant understand sentence of "YOu cannot drive the OpAmp closer than 50mv to ground, so there is a limit there."

   

Thank you.

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HeLi_263931
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Yes, I meant "24mV above Vref", this was just a typo.

   

The input signal seems OK. Whats strange is that the frequency of the output signal is only about 960Hz, this is way of from what it should be.

   

Can you do a scope shot that shows these 4 signals on one screen:

   
        
  1. Vref from the PSoC, DC-coupled, with 1V/div
  2.     
  3. Vin, DC-coupled, with 1V/div
  4.     
  5. Vout, DC-coupled, with 1V/div
  6.     
  7. Vin, AC-coupled with 10mV/div
  8.    
   

Traces 1-3 should be aligned to each other so one can see how input and output are aligned to Vref. Trace 4 is to see the input voltage in more detail.

   

To further debug this please test with a DC input to see the relationship between inout and output voltages. Also, can you attach a copy of your project (assuming its just the PGA and nothing more), by "File / create workspace bundle"?

   

To #3: The output of the PSoC OpAmps cannot create voltages lower than 50mV above GND. So when you input 10mV into an OpAmp buffer, your output will be 50mV (more or less, but thats the limitation). With low output currents you might get a little bit lower to GND, though.

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Anonymous
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4 signals on one screen are shown in the attachment

   

 1.yellow:Vref  from the  PSoC, DC-coupled, with 1V/div;

   

2.green:Vout , DC-coupled, with 1V/div;

   

3.pink:Vin, DC-coupled, with 1V/div;

   

4.blue:Vin, AC-coupled with 20mV/div(20mV/div is the limitation about my scope ).

   

 

   

my project about PGA is also seen in the attachment.

   

 

   

Thank you!

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HeLi_263931
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Hmm. Are you sure that input signal really is near Vref? From the screen its either near 2V (2 division above GND) ore near GND (when the small '3' on the left side signals where 0V for that signal is). Unfortunately I don't own a Rigol scope, so I don't know the display works there.

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EvPa_264126
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Perhaps at high magnification is needed buffer. Try these 2 variants :

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odissey1
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@499...

   

As it seems that you trying to amplify AC signal, add a capacitor on the input to cut-off DC offset. Example schematics is attached. Notice, that even with both input and reference sitting on the 1.024 V Vref, there is still some DC offset on the PGA output, which makes 2 DC-coupled consecutive PGAs practically unusable (The schematics shows solution to this). The DC offset is different for inverting and non-inverting modes (my recollection that it is less in inverting mode).

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