3 Replies Latest reply on Apr 12, 2016 11:02 AM by BoTa_264741

    Wondering: Are logic gates on design surface being optimized?


      I find myself drawing logic gates that follow my line of thinking and hopefully reflect the purpose of the logic itself (labeling nets).


      Looking at the result it is obvious that this does not result in an optimal circuit.


      Will Creator apply boolean algebra to simplify/optimize the actual logic that is programmed in the PSoC chip?


      Thanx, Marc.