Wondering: Are logic gates on design surface being optimized?

[MaJa_1553636]

I find myself drawing logic gates that follow my line of thinking and hopefully reflect the purpose of the logic itself (labeling nets).

   

Looking at the result it is obvious that this does not result in an optimal circuit.

   

Will Creator apply boolean algebra to simplify/optimize the actual logic that is programmed in the PSoC chip?

   

Thanx, Marc.

[Bob_Marlowe · Accepted solution]

Will Creator apply boolean algebra to simplify/optimize the actual logic Clear answer: Yes

   

The optimization the fitter applies are so strong that even a whole bunch of logic and components might get optimized out when you forget to connect them to a pin, thus not using the gates.

       

Bob

[MaJa_1553636]

Good to know, thanx!

[odissey1]

obiwanjacobi,

   

  I believe that optimization relies on project->build settings, if no optimization selected, no gates re-arrangement will take place.

   

see discussion in former thread:

   

http://www.cypress.com/forum/psoc-creator-software/creating-50nsec-delay-psoc3-logic-cells