Changing LUT values exceeds design

[Anonymous]

Hi.

   

I'm using the CY8CKIT-059 board for my evaluation.

   

Right now my design uses 79% of UDBs. It has many components in it, two of them are 5-in 6-out LUTs.

   

At some point I decided to change some values in them. After doing that I get the "E2071: Unable to pack the design into 24 UDBs. See the Digital Placement section of the report file for details. For additional assistance, see the Mapper, Placer, Router section in the PSoC Creator help".

   

I would like to stress that the only change between successful compilation and the above error is LUT values. All I have to do is clicking "Undo" once, and it compiles successfully again.

   

Why does this happen? How can I overcome this problem?

   

Thanks.

[HeLi_263931 · Accepted solution]

These LUTs get compiled into simple AND/OR/NOT gates, into the marco cells of the UDBs. Each MC can hold two output signals. Depending on the actual logical equations it differs how the logic can be distributed - so it might be that one UDB can hold only one signal and not two. This might leads to resource exhaustion.

[HeLi_263931]

When you are implementing a state machine in your LUT, you can try to implement them manually. (One DFF per state, a common clock, and logic for each DFF to set its state). This _might_ be more effective, but its not guaranteed.

[Anonymous]

I'm getting the same error, but with identical logic drawn a little differently. This design routes fine with 40.4% od UDBs:

   

[See Attachment 1]

   

But this design will not route due to more than 24 UDBs used.

   

[See Attachment 2]

[Bob_Marlowe]

Obviously the optimization fails a bit. You could do better using 4 LUTs.

       

Bob