PS0C3 DelSig_16Ch example project

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cross mob
Anonymous
Not applicable

I tried this project. Its seems that there is high crosstalk among the channels. If I changed the mux and ADC control to pure software, it works okay. Any idea?

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ETRO_SSN583
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I do not see example project in "Find Example Project" menu when

   

right clicking component, can you post it ? PSOC 2.1

   

 

   

Regards, Dana.

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HeLi_263931
Level 8
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Are you using the "Multi-Sample" mode? The data sheet states explicitely that, when changing the input signal in these modes, one need to stop and re-start the ADC to avoid cross-talk.

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Anonymous
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ADC is in Single Sample mode.

   

The project is available in Creator 2.1.

   


 

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ETRO_SSN583
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I did not look in detail at code, but you are inserting delay as needed for mux switching.

   

So I would ask the following -

   

 

   

1) If all inputs are tied to the same LOW Z V source, how much channel to channel variation

   

are you getting ?

   

 

   

2) Are inputs, relatively speaking, all from hi Z V sources ? Meaning are they subject

   

externally to C coupling from adjacent sources, which they would be if hi Z sourced.

   

 

   

3) How much is the variation you are seeing from what you believe should be known ?

   

In LSBs.

   

 

   

Regards, Dana.

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Anonymous
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I did not make any change to this example. The crosstalk is very bad and not only between adjacent channels.

   

 

   

After modified the example to use pure software control (ADC, AMUX), I did not encounter the crosstalk problem.

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Anonymous
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 Panson posted
Hi Panson:   

 

   

I need to do 32 channel 16 bit ADC project , can you give me the reference of your design?
Thank you very much !

   

My E-mail: lo_xiaohua_ve@yahoo.com.cn

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Anonymous
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Dear All:

   

The mux inputs to settle when switching between inputs Channel , how much time is necessary to channel switching???
thanks!

   

XH

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ETRO_SSN583
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I am not aware there is a settling time spec.

   

 

   

But you can do an analytical calculation, mux and ADC represent a series R-C network.So

   

imagine a voltage source feeding a R, junction of R and C goes to A/D, other side of this

   

parasitic C goes to ground. If you apply an analytical step input into it, the range of your

   

inputs, you can calculate using exponential rise equation, solving for a final value of

   

Vinmax - 1/2 lsb equivalent voltage. That will give you settling time to 1/2 lsb.

   

 

   

Defining equations here - http://en.wikipedia.org/wiki/RC_circuit

   

 

   

Regards, Dana.

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HeLi_263931
Level 8
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In continuous mode, the PSoC3 CY8C38 family data sheet states that one need to wait for 3 conversion times after switching (part 8.2.2.2). In such cases it is better to use the multi-sample mode.

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HeLi_263931
Level 8
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Note that the reason for this wait time after channel switching (in continuous mode) is the internal state of the ADC. It maintains a decimator, which needs 3 conversions to be primed properly. So if you read results too early, you get data from the former channel.

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ETRO_SSN583
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The internal ADC requirements for delay do not obiviate the need to manage

   

settling time in the signal path. Clearly you have to apply a settled input to

   

the ADC if you are seeking accuracy.

   

 

   

Regards, Dana.

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Anonymous
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Settling time aside, cross talk could result from two input lines running parallel and signals couling through parasitic capacitance between lines. What is the input to mux channles? If all inputs are constant voltages, then this possibility could be eliminated.

   

 

   

To calculate the settling time, you can use RC circuit analysis. R would roughly be output impedance of the source added with mux resistance of psoc (this looks to be present in psoc3 datasheet electrical characteristics - 706 ohm for mux bus) and trance resistance (if significant). C would be addition of trace capacitance, pin capacitance.

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Anonymous
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Thanks for your reply,

   

In this example project , have a AMuxHw module, I'd like to know the multiplexing switch channel switching time, for instance from channel 1 change to channel 2 to the output stability time? Because must wait until channel switching stable made after ADC sampling to get correct results.

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ETRO_SSN583
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As previously posted. One other alternative, you could easily devise a test,

   

with a 0 to Vref step into A/D by grounding one mux input, setting other to Vref,

   

and step mux to Vref channel  and perform a loop measuring deviation from one

   

measurement to next, until change meets some criteria, like < 5 LSB. But this only

   

works if settling time >> A/D measuring time, otherwise you are under sampled.

   

 

   

Prior post -

   

I am not aware there is a settling time spec.

   

 

   

But you can do an analytical calculation, mux and ADC represent a series R-C network.So

   

imagine a voltage source feeding a R, junction of R and C goes to A/D, other side of this

   

parasitic C goes to ground. If you apply an analytical step input into it, the range of your

   

inputs, you can calculate using exponential rise equation, solving for a final value of

   

Vinmax - 1/2 lsb equivalent voltage. That will give you settling time to 1/2 lsb.

   

 

   

Defining equations here - http://en.wikipedia.org/wiki/RC_circuit

   

 

   

Regards, Dana.

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Anonymous
Not applicable

 Typically Analog HwMux would take about two cycles of input clock - One clock for breaking the existing connection and another clock period for making the new connection.

   

 

   

-

   

Kishore.

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