A problem about EZ-USB FX3 Slave FIFO

[Anonymous]

Hi，

   

  I'm trying to run the example of Slave FIFO in BulkLoop Mode ,but use our Altera FPGA Board. I have some problems with the FlagA & FlagB. Here I set the FlagA & FlagB as Full-Flag and Amost-Full-Flag of Thread_0 which is getting data from FPGA and sending to PC.  Here my Fifo databus is 16bit , the watermark of Thread_0 is 6 and the watermark of Thread_3 is 2.

   

Here is my problems:

   

 1.  I find the FlagA & FlagB both high in initial state When I send a text File Out(size 512) through the Control Center. Is that right?

   

2.  Through the waves, I find the FlagA & FlagB doesn't change when Status Machine is running at Bulk_Loop_Write. It cause Status Machine couldn't run to next state. Why FlagA & FlagB doesn't work while FlagC & FlagD work well?

   

Thank for your help!

   

Tomsen

[Anonymous]

I understand that you are associating FLAGS A and B with Thread 0(Socket 0). The FPGA is writing data in to Socket 0, hence the flags associated with socket 0 will show the FULL status of the buffers associated. By defaults these flags are active low. So at the start, when there is no data is written by the FPGA in the buffers the FLAGS A and B will be high. This is correct.

   

When we are sending data through the USB side,i.e. for the FPGA to read, then the FLAGS will monitors the EMPTY status of the buffers. When the FPGA is reading data from the FX3 buffers, the status of the FLAGS associated with Socket 0 will not change. In this case , the status of the FLAGS associated with Socket 3 will change.

   

What is exactly the issue you are facing?

[Anonymous]

Hi Kashyap, my issue is I could not capture the FLAGS A and B to be low when the FPGA is writing data in to Socket 0.  The #SLCS and #SLWR are setted low when the FPGA start to write data, the other singals are setted high. You mean that the FLAGS A and B will be high if no data is written by the FPGA in the buffers, what's wrong with my sequential?  Is there any details I should pay attention to ?

   

Best regarsd,

   

Tomsen

[Anonymous]

Yes, Initially these FLAGS will be high (as they are active low, by default). Once the buffers are filled by the FPGA or the watermark value has been hit , these will become low.