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Hello Every One,
I am again having a problem and i don't know why 😞
The Program is very simple:
I build a program for a Bridge. What i am doing is described below:
1. I am using a waveDAC in order to excite my bridge.
2. output of the bridge is comming into a 12-Bit SAR ADC.
3. output of the ADC if going to the LPF.
4. LPF output is being written into DAC.
Problem: The problem is that my final output is not correct. I am feeding a 10 Khz signal and my cuttoff frequency is 15Khz. But i am not getting a sine signal as i supposed to get.
I also attached and output pic and my program file.
Yellow wave: Excitation Signal.
Purple or Pink Wave: Signal entering into ADC.
Blue Wave: Filter Output seeing through DAC Ch1.
Looking forward for your suggestions!
Best Regards
Awais
Solved! Go to Solution.
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PSoC 5LP
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The filter delivers signed values, the DAC only accepts positive integers. You need to convert (add 128) the filter output to DAC manually. Will be quite tough with a sampling rate of 72ksps. A way out could be to build a DMA capable component that does the conversion using an UDB and use another DMA for each channel. Not easy, but that will work definitively without any timing constrains.
Bob
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The filter delivers signed values, the DAC only accepts positive integers. You need to convert (add 128) the filter output to DAC manually. Will be quite tough with a sampling rate of 72ksps. A way out could be to build a DMA capable component that does the conversion using an UDB and use another DMA for each channel. Not easy, but that will work definitively without any timing constrains.
Bob
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Thankyou Bob for your reply.
How about if i use an interrupt signal in order to transfer data (added 128) from filter to dac instead of DMA? Would be helpful?
And "to build a DMA capable component"
How i can do that? you mean in software?
Awais
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72k interrupts per second can be VERY tight! Will need some thinking, probably polling is faster.
Building a new component needs some knowledge. There is some documentation (already installed) as the "Component Author Guide" and the "Warp Verilog Reference Guide". Both installed under the start menu in Cypress->PSoC Creator 3.3>Component Development Kit". Will cost you the rest of the week to read... 😉
Bob
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Rest of the week 😮 !!! OMG
Ok Thankyou Bob 🙂
Awais
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In your handler you do not care that you will get interrupts from channel A and channel B and not necessarily at the same time. So you will run up to 144000 interrupts per second, quite a lot.
There is a status register for the filter component which you should read and decide which interrupt has fired or rather which channel is ready to read data off.
Bob
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Thank you Bob for your reply. I get your point partially.
Can you please upload the program with your changes in it?
It would be great 🙂
Regards
Awais
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I do not have a program to upload.
Bob
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I did not make changes to your program, that is up to you.
Bob