psoc4 counter clear interrupt

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
Anonymous
Not applicable

I am new to interrupts and was playing recent days to improve on a previous design of timer-box.

   

I successfully got some psoc4 demo with gpio pins as source and it worked. Now I am on UDB elements and irqs, however unlike the more general PWM based counter the most basic Counter lacks generated functions to reset interrupts. How do you achieve it?

   

So far I have:

   

    uint8  c_r =  Counter_1_ReadControlRegister();
    //c_r &= ~ 1u;
    c_r |= 1u;
    Counter_1_WriteControlRegister(c_r);

   

Are those the right API functions and the value considering I am interrupting on compare of the counter! I got a bit lost with all the macros in the gen files maybe someone can give tips, 1u I derived from : Counter_1_STATUS_CMP_INT_EN_MASK;

   

 

   

Maybe it is a very noob question, btw so far the docs for psoc4 interrupts were really helpful.

   

CHeers

0 Likes
4 Replies
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

For clearing the interrupts the timer component already cares for. Just read the status register using Counter_ReadStatusRegister(). This will clear the bits that have caused an interrupt. See Datasheet page 14.

   

 

   

Bob

Anonymous
Not applicable

ahh RTFM again 🙂

   

thanks Bob ( I knew you would be fast on it) 😛

   

I've also found something similar after some googling (know how entry for psoc3/5)

   

So yes automagically ReadStatusRegister() did the trick!

   

However, I must say this API is quite poor:

   

1) It is far from obvious (just the opposite) that a mutating function is called get* and also from the tech-sheet : " * Side Effects:
*   Status register bits may be clear on read. " frankly maybe is the last word I look to see in tech-docs 😄

   

2) It is quite inconsistent considering how irqs are cleared for GPIOs and TCPWM, examples I've seen so far.

   

 

   

Maybe I might switch to TCPWM or something similar, since I just want front/back period counts and interrupt on last/first.

   

It is already the 2nd time I got bitten by Counter element (before was pure GUI artefact) (in psoc-creator 3.2sp2 it is fixed)

0 Likes
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

There is a reason for the "strange" implementation: UDB.

   

An UDB allows to be used for nearly everything digital, though it is not an FPGA. It contains a programmable ALU, some registers, two FIFOs, a PLD area and a bunch of routable signals. You (rather: Cypress) can build an UART from it, a sophisticated counter component or a random number generator or..., or... or...

   

So best will be to use the fixed function based components first. When the project needs more resources use the more versatile UDB based ones.

   

Still at need of a component that isn't there? After a long, steep and winding  learning-curve you may even create own components out of UDBs using a HDL (Hardware Description Language) named Warp Verilog. Everything already installed on your PC, including the documentation.

   

 

   

Bob

0 Likes
Anonymous
Not applicable

In a simpler way, I have done

in the interrupt:------------------

CY_ISR(ISR_Interrupt)

{

    #ifdef ISR_INTERRUPT_INTERRUPT_CALLBACK

        ISR_Interrupt_InterruptCallback();

    #endif /* ISR_INTERRUPT_INTERRUPT_CALLBACK */

    Counter_ReadStatusRegister(); // This will clear the interrupt if set

    txungs = Counter_ReadCounter();

    txung=65535-txungs+3;//+3 is later timer

    Counter_WriteCounter(65535);//reset counter before repeat

}

in main:--------------------

int main(void)

{

    Counter_Start();

    UART_Start();  

    PWM_1_Start();

    ISR_Start();

    CyGlobalIntEnable;

    for(;;)

    {   

        sprintf(strings,"%d ",txung);

        UART_UartPutString(strings);

        CyDelay(100);

    } /* End of infinite "for" loop */

}

Capture.PNG

Good luck to you.