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Anonymous
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Jun 06, 2016
01:48 AM
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Jun 06, 2016
01:48 AM
Hi:
I use FPGA to transfer data with USB. TX_DATA is ascending series . But i receive the data isn't. I don't know where is wrong. who can help me?
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Anonymous
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Jun 08, 2016
11:59 AM
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Jun 08, 2016
11:59 AM
Hi,
Please check if the SlaveFifo interface signals are in accordance with what is expected. Obtain a scope of signals and examine.
Also, you can use the UART Debug Prints to check if there is any issues.
Regards,
- Madhu Sudhan
Jun 10, 2016
05:37 AM
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Jun 10, 2016
05:37 AM
Thanks for the answer. I have solved the problem. Thank u very much!