Generating multiple waveforms with fixed phase relationships

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Anonymous
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I need to generate 3 sinusoids at around 30KHz, with relative phases of 0, 90, and 180 degrees.  I've experimented with the WaveDac component, clocking it myself, and only turning the clock on after all three software initialization commands have been executed, but this still seems to result in the relative phases drifting over time.  I assume this is due to the DMA having to wait from time to time.

   

So I've resorted to using VDAC8s, along with the Sin8 component that was shared on these forums a while back.  (Sin8 a hardware lookup table, I'm attaching a block diagram, along with a project that implements the scheme with 4 DACs rather than 3.

   

I've gotten this to work, but it seems to have some mysterious timing issues/marginalities.  For example, when I add a shift register that is not in any way connected to the waveform generation, the signals get corrupted.

   

So I have two questions:  (1) Is this approach misguided in some way? and (2) is there a better/easier way to generate the signals I need?

   

 

   

thx

   

 

   

Mike Boich

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odissey1
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First comment on KBA 1000 replies posted 750 replies posted

Mike,

   

I am the author of that sine8 component, which was used in the project. I reworked sine8 component to better suit your goal by adding extra "phase" input. This way all timing will be syncronized better (look at the results->timing report.html). Attached is archived project and demo screenshot. With 5-bit sine table, project generates four sine waves shifted by 90 deg to each other at 197 kHz with no problem.

   

To have adjustable output frequency the BasicCounter can be replaced with DDS24 component, which you can find here:

   

http://www.cypress.com/forum/psoc-community-components/dds24-24-bit-dds-arbitrary-frequency-generato...

   

   

   

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odissey1
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First comment on KBA 1000 replies posted 750 replies posted

Mike,

   

I am the author of that sine8 component, which was used in the project. I reworked sine8 component to better suit your goal by adding extra "phase" input. This way all timing will be syncronized better (look at the results->timing report.html). Attached is archived project and demo screenshot. With 5-bit sine table, project generates four sine waves shifted by 90 deg to each other at 197 kHz with no problem.

   

To have adjustable output frequency the BasicCounter can be replaced with DDS24 component, which you can find here:

   

http://www.cypress.com/forum/psoc-community-components/dds24-24-bit-dds-arbitrary-frequency-generato...

   

   

   

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Anonymous
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Odissey,

   

 

   

Thanks for creating the sine8 component in the first place, and thanks for the phase feature!  That's just what I need. 

   

 

   

Mike

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EvPa_264126
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I had a similar problem.
I used DMA:  DMA8x3.cywrk.zip

   

 

   

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Anonymous
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Pavloven,

   

Thanks for your reply. I wasn't sure if the DMA would be 100% deterministic or not, which is the nice thing about the sine8 component. The DMA is nice in that it avoids the issue of having to multiplex the DAC bus, though. 

   

 

   

Mike

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odissey1
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        According to Cypress, DMA transfer from buffer to VDAC8 takes 14 CPU clocks. My experience is that number needs to be doubled to have guaranteed timing (otherwise some cycles are getting missed occasionally). So for 48 MHz CPU clock, 32 points per waveform and 4 DACs, maximum reliable frequency is: 48E+6 / 14 / 2 / 32 / 4 = 13.4 kHz.   
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Anonymous
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One other thought/question.  I now realize that I only need two Dacs at any given time, but multiplexing the DAC bus still means that the two DACs are still going to be strobed a half sample apart (2*pi/64 in the case of the 32 bit table), which creates a phase error.  The results are still acceptable for my application, but if I wanted optimal results, I could create a second Sin8 component with the lookup table shifted by 2pi/64.  Then (after the reconstruction filter), the two signals should be in exactly the desired phase relationship.  Does that make sense?

   

 

   

(For what it's worth, I'm using the sinusoids to create Lissajou curves on an XY display, and the 1/2 sample difference affects the roundness of circles by the amount shown in this animated GIF:

   

   

Worse yet, the effect on negative-sloped lines (represented by Sin(x),-Sin(x), is shown in the bottom image.

   

   

   

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Anonymous
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Or, having thought about it, I can just use a 64 entry Sin8 table, and have the first VDAC reading the even entries, and the second VDAC the odd entries.  That should eliminate the phase error that comes from the offset timing of the two VDACs.  And for my application, the first channel needs to be a sin, and the second needs to be either 0, 90, or 180 degrees out of phase with the first.  So I'm thinking something like this should work, though I'm not in a place where I can actually test it.  (And LUT_1 is overkill now.  I can just use the low order counter bit to strobe one DAC, and the add an inverter to strobe the other).

   

   

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odissey1
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First comment on KBA 1000 replies posted 750 replies posted

Mike,

   

I will look into it this weekend. The easiest way would be to use two sine lookup table. At size 32 they will fit PSoC5. Set one phase for Sine output and another for Cos.

   

Second approach would be to use a single sin8 lookup table make, but to strobe sin and cos output with time interval much shorter than 1/32 of period to minimize phase error. The VDAC8 can handle strobe intervals as short as 100-200 ns, so all you need is to form right sequence of the "strobing" pulses.  

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Anonymous
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Odissey,

   

I eventually realized that the 64-entry table contains the values that would be needed for the offset 32-entry table.  So my latest attempt uses a 64 entry Sin8 component, and a 6 bit counter.  All 6 bits go to the sin8 component, and the LSB also triggers the strobe, so that one DAC gets the even number table entries, and the other gets the odd.  I'm thinking that this eliminates the phase error, rather than trying to make the error smaller by strobing the DACS in quick succession.  The first DAC is a sin, and the second is offset 0,90,180, or 270, depending on the contents of the control register.  (Thanks again for adding the phase input!)

   

I'll home from travelling and able to test this on Monday.   Thanks for your help and please let me know if you see a flaw in that reasoning.

   

Mike

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odissey1
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mike,

   

I explored one approach, trying to minimize phase shift between sine outputs by sampling each value at next clock (~30 ns apart). Two projects attached: for 64- and  32-poins per period, and 1/32 phase shift in between points. At 64 ppp phase shift is within the noize, at 32 ppp there is some noise observed due to output quantization. Adding RC filter will probably eliminate this. Pictures and projects are attached.

   

Another alternative might be utilizing 2 sine tables, 2 output buses and 2 external DACs (DACs on PSoC share a single bus, so they can't be updated simultaneously). I used self-made R-2R DAC using 0.1% resistors, and it works better than VDAC8 at hign frequencies. 

   

   

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Anonymous
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Yes, period/2048 certainly kills the problem for my purposes!  Thanks.

   

 

   

- Mike

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Anonymous
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Simple sine and cosine - not best for this thread but usefull

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Anonymous
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Thanks for all of the responses.  I've gotten my project working, though I still need to chase down some stray noise to get it looking really good.  Here is a video for anybody who is curious:  https://dl.dropboxusercontent.com/u/27276291/DSCF1900.m4v

   

 

   

- Mike

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JLS1,

   

glad to see you again on this forum and  interesting implementation of the Smith-Gordon oscillator. I also played with it before and found some issues with stability and output frequency ambiguity due to the finite word length. But for this application this might be a perfect match.

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odissey1
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Very cool project indeed!

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