Build a Verilog component

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Anonymous
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Hello all, I want to build a component which will receive data from adc. After receive data it will take avarage of data and send it to an array. Actually it would work like a DMA component. My problem is I don't have any experience with them. There are some examples about verilog but I really need help about part of DMA. Anyone has a example or any note how can I do it and how can I add it on my project. 

   

If this seems so hard or impossible, can you help me about the this process. As I give detail to my project, I am receiving data from ADC and I send them to emfile via DMA. As you understand, my for structure is fully empty. DMA's do all job. But I need to process this data. Process are avarage, min max value etc. Do you have any idea about that. 
 

   

Thanks 

   

Burak

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5 Replies
Bob_Marlowe
Level 10
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Could be difficult, because emfile does not have got a DMA receiver. There will be something in your for-loop, at least a write of a buffer to emfile.

   

 

   

Bob

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Burak,

   

Can you elaborate on those questions: Do you need a moving  average from SAR- or DelSig_ADC? At what data rate / bit width? How many data points need to be averaged before saving?

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Anonymous
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I am taking current value from device. I need to average of this current value. Actually not just average also min value, max value, rms etc. My adc is 16bit and sample rate is 43750 sample per sec. 

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Anonymous
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At least can I do a component which takes data from dma and process them(find min value etc...) and send them to an array ?

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Burak,

   

I was thinking originally that you plan is to using PSoC's SAR_ADC for ~1Ms data acquisition and custom verilog component for averaging only. That can be done (but will eat away ~50% of the PLD). But "RMS & etc." will not fit (multiplication in Verilog is costly).

   

If your data rate was in ~10ks range, the CPU could handle that for sure. Maybe it can even handle this at ~40ks, which is definitely worth trying first. Hope you don't plan saving all data at full speed, it has to be decimated first, so that external memory could handle that.

   

At ~40ks speed,  the DFB can be used to offload processing from CPU (again, no custom component is required). But it has to be programmed in assembly, which won't be easy. As an example take a look on this original article by Aubrey Kagan in PlanetAnalog (measuring RMS using DFB component and custom assembly code):

   

http://www.planetanalog.com/author.asp?section_id=3140&doc_id=564228

   

or re-post on Cypress website:

   

https://cypress.hackster.io/antedeluvian/measuring-an-rms-signal-on-a-psoc5-a9fa6d?ref=platform&ref_...

   

 

   

Try to re-use / modify this RMS project for your goals. It has RMS portion already, you can use second DFB channel for averaging and min/max. 

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