PSoC4 TCPWM clock connection with LFCLK

Tip / Sign in to post questions, reply, level up, and achieve exciting badges. Know more

cross mob
IoVo_297831
Level 4
Level 4
First like received

Hi all,

   

I would like to if there is any way to connect the LFCLK to the TCPWM block in PSoC4 BLE.
Is there also any way to connect the clock input of the TCPWM block to another signal except of clock blocks?

   

Our application requires a continuously running timer, even when the device is in sleep mode.
The optimal solution was the TCPWM block to be able to be clocked by the LFCLK or the OV output of another TCPWM block.

   

Should I continue searching on that or should I change direction?

   

Thank you in advance,

   

Best Regards,
Yiannis

 

0 Likes
1 Solution
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

The TCPWM as the UDB based components do need the HFCLK to function correctly. The only device using LFCLK would be the 3 WatchDog Timers (WDT) which can be configured easily to get the PSoC4 out of deep sleep.

   

What is the needed output frequency for your "continuously running timer"?

   

 

   

Bob

View solution in original post

0 Likes
6 Replies
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

The TCPWM as the UDB based components do need the HFCLK to function correctly. The only device using LFCLK would be the 3 WatchDog Timers (WDT) which can be configured easily to get the PSoC4 out of deep sleep.

   

What is the needed output frequency for your "continuously running timer"?

   

 

   

Bob

0 Likes
IoVo_297831
Level 4
Level 4
First like received

Bob thank you much for your reply.

   

The timer is required to work as a chronometer.
The overflow should happen after days (or at least several hours) and is required to be able to read the timer value in miliseconds at any time.
It is not required the interrupt, just counting with the ability to read the timer.
Also, it is not required to wake up the device from deep sleep, just keep counting at deep sleep and when the device wakes up due to other events, to be able to read the count value.

   

Using the WDT timers, I think there is not the ability to read their values.
I found that counter block can accept LFCLK as clock input but I would also want the count input to be connected with LFCLK.

   

This task would not be difficult if the counter could stop its operation during deep sleep.
But since it works as a chronometer, it should work when the device gets into deep sleep.

   

Best Regards,
Yiannis

0 Likes
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Depending on the precision of the 32kHz crystal the WDT is quite precise. There is not muck overhead in programming when the WDT interrupts every second, you can read the contents of a WDT timer at any time 😉 using CySysWDTGetCount() as described in the "System Reference Guides" Low frequency Clocks for PSoC4.

   

 

   

Bob

0 Likes
IoVo_297831
Level 4
Level 4
First like received

Thanks Bob, I had overlooked that function.

   

I should have found it without asking, sorry for that.

   

Best Regards,
Yiannis

0 Likes
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

A PSoC is a very complex thing existing in families with different capabilities and different implementations of similar components. When I happen to know a function and you do not, that is not a reason for an excusion. Yesterday I programmed an RTC and I had to use that API.

   

 

   

Bob

0 Likes

Thanks anyway.

   

Best Regards,
Yiannis

0 Likes