2 Replies Latest reply on Aug 14, 2016 7:38 PM by userc_39763

    GPIF pclk timing question

    userc_39763
    userc_39763 Aug 18, 2017 1:12 PM

      The sensor:MT9M001.The output data[0:9] is valid on the falling edge of clk.

         

      FX3 GPIF setting:16bit data bus; active clock edge:negative.....

         

      When the PCLK is 27MHz, the image is normal; but when the PCLK is 48MHz,the image is sideling.

         

      The PCLK depends on the mclk of sensor.

         

      I don't konw why? there is some problem of GPIF timing?

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        • 1. Re: GPIF pclk timing question
          madhul_36
          madhul_36 Aug 14, 2016 1:45 AM (in response to userc_39763)

          Hi,

             

          What is the frame rate at 48 Mhz? Can you please check if you have any buffer overflow errors? (CyU3PDmaMultiChannelCommitBuffer Api returns error).

             

          Regards,

             

          -Madhu Sudhan

          • 2. Re: GPIF pclk timing question
            userc_39763
            userc_39763 Aug 14, 2016 7:38 PM (in response to madhul_36)

            I have checked. There is no buffer overflow errors.

               

            The resolution of sensor: 1280x1024. The frame rate is 30fps at 48MHz.

               

            I use the usbmon to monitor the amount of usb bus. The result is as follows:

               

            1) 27MHz: the amount of the usb bus is 2621440=1280*1024*2, it is right, the image is normal.

               

            2) 48MHz: the amount of the usb bus is 2623488>1280*1024*2, it is incorrect, which results in the sideling image.