Hardware mux timing

[jakac_1482786]

I am trying to design a circuit that oscillates at ~48 kHz using hardware muxes and clocks.  A picture is attached.  PSoC lets me build this design using 2 clocks that are synched on the two muxes.  (Master CLK is 48 MHz).  It keeps giving me a Warning 1350:Asychronous paths exist from clock2(routed) to Clock1. 

       

Does anyone know why this is happening and how to resolve it?

   

Thanks!

   

jk

[Bob_Marlowe]

I usually tried using a pulse sync component.

       

Bob

[jakac_1482786]

Is that a PWM?

[Bob_Marlowe · Accepted solution]

No, it is a pulse sync component. Creator -> Component catalog -> Digital -> Utility -> Sync

       

Bob