Hi.
I'd like to implement slavefifo IN wih FPGA. then I've just found as below code from AN65974.
module slaveFIFO2b_fpga_top(
reset_in_, //input reset active low
clk, //input clp 27 Mhz
// sync,
fdata,
faddr, //output fifo address
slrd, //output read select
slwr, //output write select
flaga,
flagb,
flagc,
flagd,
sloe, //output output enable select
clk_out, //output clk 100 Mhz and 180 phase shift
slcs, //output chip select
pktend, //output pkt end
mode_p,
PMODE,
RESET,
// tri_state,
// PMODE_2 //used for debugging
);
But I'm not sure below 1 port what should I do with that
mode_p
Might be, I believe that above 1 port is connected with FX3 board. but I'm not sure and what am I supposed to with 1 port. Even there is nowhere in the CYPRESS documents about mode_p .
Does anyone know how to connect the mode_p with FPGA and FX3 board?
