5 Replies Latest reply on Jan 24, 2017 7:33 AM by duno_297731

    PSOC with verilog, how big a design can one make?

      I wonder how big a design one can make with the UDB in the PSOC5 LP. I use Xilinx Spartan/Virtex parts often but PSOC5 is very interesting to study. How big can one make with a single UDB in terms of ASIC gates? Can 24 UDB be combined to make a bigger design?