16FX: Interrupt Evaluation Order of same priority level Interrupts

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LoGr_1658566
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Hello,

   

The 16FX MCU uses an Interrupt Vector Table where each Vector has its own address, so for the MB96F338USA the Table starts with Vect#0 (CALLV0) and ends with Vect#122 (USB MiniHost 2)

   

When several Interrupts of the same priority level are pending, which one is processed first? (Is evaluations starting with highest or lowest Vect#?)

   

Regards,

   

Lorenz

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HolgerW_56
Employee
Employee
25 solutions authored 10 sign-ins 5 sign-ins

If multiple interrupts occur on the same level, the IRQ with the lowest interrupt number is executed first.

   

(See 16FX/MB96300 Super Series Hardware Manual, chapter 3 section 3.6 paragraph 'Structure of the hardware interrupt system')

   

Regards,

   

Holger

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LoGr_1658566
Level 1
Level 1
First reply posted First question asked

Hello again,

   

an example from my Interrupt Vector List

   
;------------------------------------------------------------------------------------------------------------------ ;    Datatype   Interruptserviceroutine                 Vect#   Offset  Funktion    Beschreibung ;------------------------------------------------------------------------------------------------------------------
   
    .DATA.L     _PWM_ICU_4_isr                      ;   65      0x2F8   ICU4        Input Capture Unit 4     .DATA.L     _PWM_ICU_3_isr                      ;   64      0x2FC   ICU3        Input Capture Unit 3     .DATA.L     _PWM_ICU_2_isr                      ;   63      0x300   ICU2        Input Capture Unit 2     .DATA.L     _PWM_ICU_1_isr                      ;   62      0x304   ICU1        Input Capture Unit 1     .DATA.L     _PWM_ICU_0_isr                      ;   61      0x308   ICU0        Input Capture Unit 0
   

If all ICU Interrupt have the same Level and a request occurs at the same time, which one is executed first?

   

regards,

   

Lorenz

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HolgerW_56
Employee
Employee
25 solutions authored 10 sign-ins 5 sign-ins

If multiple interrupts occur on the same level, the IRQ with the lowest interrupt number is executed first.

   

(See 16FX/MB96300 Super Series Hardware Manual, chapter 3 section 3.6 paragraph 'Structure of the hardware interrupt system')

   

Regards,

   

Holger

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thank you for clarification,

   

regards,

   

Lorenz

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