2 Replies Latest reply on Nov 21, 2016 2:20 AM by jerome.hiebel_1699481

Reduce KitProg's 4.5MHz clock speed

jerome.hiebel_1699481 Nov 18, 2016 2:06 AM

Hi,

I have the CY8KIT-042-BLE with onboard kitProg, I am trying to debug an CYBLE-012011-00 that I wired to J11.

Communication fails almost all the time, wires are certainly too long (40mm). It's sometimes recognized but the looses the communication.

By default PSoC programmer and PSoC Creator have SWD set to 1.6MHz. I reduced the second to 0.2MHz but setting doesn't seem accessible for the first. Still doesn't work.

Then I probe SWDCLK: it's bursting at 4.5MHz !!! no matter the setting, it's just trying to communicate at 4.5MHz, how can I reduce this?

Thank you,

Jerome

1. Re: Reduce KitProg's 4.5MHz clock speed

AnjanaM_61 Nov 21, 2016 2:15 AM (in response to jerome.hiebel_1699481)

Hi Jerome,

Please avoid using long wires for SWD programming. Because it may effect the clock speed. Use small wires as possible.

Also if you select low frequency, then it will set for low frequency , it won't be showing 4.5MHz. Please check whether the programmer settings are correct.

Thanks,

Anjana
Like Show 0 Likes(0)

Actions
2. Re: Reduce KitProg's 4.5MHz clock speed

jerome.hiebel_1699481 Nov 21, 2016 2:20 AM (in response to AnjanaM_61)

Thank you Anjana for your reply, my wires are not long. Where do you select "low frequency" ? What are the "correct" settings? Thank you. Jerome
Like Show 0 Likes(0)

Actions

Go to original post