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Hi,
I did a custom component with a State Machine that goes from one state to the next one on every rising edge of the clock input, everything run as expected using a clock component at the clk input but i would like to feed the clk using the output signal of a comparator, this seems not possible, the error suggest me to add the UDBClockEn component between the comparator output and the clk input.
I did so, connected a logic high to the enable input of the UDBClockEn and the comparator output to the ClockIn input, sadly i can clk not connect anything on the ClockOutput so i can not debug the behavior.
I remember reading somewhere that the clock signals on PSoC5LP can be provided by "any" digital signal, but i don't remember if it can be perfect %50 of duty cycle.
So my question is, any thoughts on how to solve this problem? maybe another way to generate a clk from the comparator output?
The frequency of the signal generated by the comparator output is random, that's why i would like to use it as clock source and not a proper clock component.
The project it's attached so maybe you can take a look.
Thanks in advance
Carlos
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carlos,
without knowing all details of your measurements, instead of two comparators, can you simply amplify analog signal e.g. 100x times so it becomes fully saturated with fast transitions from 0 to 5V, becoming, almost like a "digital" signal? Then it can be additionally passed through single comparator for further conditioning.
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The problem is that i want to clock the custom component only on the rising edge of the comparator output, i don't want to use extra clocks, that's why i was looking to clock the custom component with the comparator output signals.
After posting the question i attached a logic analyzer to the comparator outputs and the upper one seems really noisy (see attached image), and also found a EEVBlog video about comparators and schmitt triggers [1], that implementation seems interesting, i will try to do it, it uses just 1 comparator and 3 external resistors, instead of 2 comparators and 2 VDACs as my first try.
Did a quick test using the onboard switch to provide the clock (see attached project), with this i "confirmed" that any digital signal of any duty cycle can be used as clock source for UDB components, the switch is debounced so i ended up using a clock component, but the signal looks clean on the logic analyzer, so the problem on the first project seems to be the noisy signal output of the comparator, now i can follow with the datapath programming and solve noise on the comparator output later lol.
Thanks for the answer, will post any follow-ups.
Carlos
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carlos,
without knowing all details of your measurements, instead of two comparators, can you simply amplify analog signal e.g. 100x times so it becomes fully saturated with fast transitions from 0 to 5V, becoming, almost like a "digital" signal? Then it can be additionally passed through single comparator for further conditioning.