Anonymous
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Dec 16, 2016
04:45 AM
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Dec 16, 2016
04:45 AM
Hi guys,
I have build a new component with the UDB Editor. Now I try to parameterize the data path width.
With varilog this can be done through defining a hardware parameter and separate the code with a if else construct.
But for simplicity I'd like to use the UDB Editor and with this graphical tool I do not find a solution for the problem.
Please Help!
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PSoC 5LP
3 Replies
Dec 16, 2016
06:35 AM
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Dec 16, 2016
06:35 AM
Welcome in the forum, Michael.
This will not work using UDB editor, must be done in verilog,
Bob
Anonymous
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Dec 16, 2016
09:01 AM
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Dec 16, 2016
09:01 AM
Hi,
thanks for the ultra fast answer! I feared that I will get such news 😞
Anyway than I have to edit the varlog file at the end.
Dec 16, 2016
10:18 AM
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Dec 16, 2016
10:18 AM