Sorry for the late response.
Both SRAMs can be used for code execution and data storage, but there are few things to mention:
- SRAM1 ist not directly connected to I- and D-Bus, thus code execution might be slightly slower.
- When using both SRAMs for data storage, a variable should not be placed partially in both SRAMs.
For example : 32bit access to 0x1FFF_FFFD
Expected access : 0x1FFF_FFFD, 0x1FFF_FFFE, 0x1FFF_FFFF, 0x2000_0000
Real access : 0x1FFF_FFFD, 0x1FFF_FFFE, 0x1FFF_FFFF, 0x0000_0000 (wrap around)
See also Chapter 14.9 in: http://infocenter.arm.com/help/topic/com.arm.doc.ddi0337e/DDI0337E_cortex_m3_r1p1_trm.pdf
Because of the second behavior and the precautions that have ot be made SRAM1 is not used in the default linker files.