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hi,all
I use ep0 to send a vendor command, I use vs2012 and x64 platform,my code like follow:
CCyUSBDevice *USBDevice = new CCyUSBDevice(NULL);
// Just for typing efficiency
CCyControlEndPoint *ept = USBDevice->ControlEndPt;
ept->Target = TGT_DEVICE;
ept->ReqType = REQ_VENDOR;
ept->Direction = DIR_TO_DEVICE;
ept->ReqCode = 0x05;
ept->Value = 1;
ept->Index = 0;
unsigned char buf[512];
ZeroMemory(buf, 512);
LONG buflen = 512;
ept->XferData(buf, buflen);
i found when i debug these code, these value is not changed,but when i fix it in memory by hand,then it normal,and can send to device,why?
thank you very much;
Andi
Solved! Go to Solution.
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The buf will contain data sent from the USB device responding to the XferData. Did you make sure the device is recieving the XferData with correct data? I see that the direction is "DIR_TO_DEVICE", so it is for sending the data to the device (not receiving back). You can change the direction in the call, also you will need to handle this in the device frimware
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The buf will contain data sent from the USB device responding to the XferData. Did you make sure the device is recieving the XferData with correct data? I see that the direction is "DIR_TO_DEVICE", so it is for sending the data to the device (not receiving back). You can change the direction in the call, also you will need to handle this in the device frimware
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Thank you for your response;
EP0 transceiver is now no problem.
But there is a new question, i hope to get your guidance.
My own circuit board, using slave fifo 32 bit mode, 100Hmz clock, provided by the pib to FPGA, I configured the watermark value as follows:
CyU3PGpifSocketConfigure (0, CY_U3P_PIB_SOCKET_0, 6, CyFalse, 1);//FPGA->USB
CyU3PGpifSocketConfigure (3, CY_U3P_PIB_SOCKET_3, 6, CyFalse, 1);//USB->FPGA
I would like to read from the PC side of different lengths of data, each time before reading, I will tell the FPGA the read length,alway 2^n,max is 8192 bytes. FPGA will report the length of the data I hope, but I found a problem, in different lengths of data reported Switch the gap, the occasional PC will receive all the 0 data, then i check the EP / DMA status is normal. But receive a PIB reported the error: CYU3P_PIB_ERR_THR0_WR_OVERRUN
I do not understand why?(FPGA report every packet as a brust)
Is it that I need to reset the watermark value every time I tell the FPGA to switch data length?
If yes, how do i do it?
Thank you!