using SP605 instead of SP601 in AN84868 - Configuring an FPGA over USB Using Cypress EZ-USB® FX3

[ritu_2178811]

Hello,

   

Can we use SP605 instead SP601 in the AN84868. The meazzine connectors have the same pinout so I think that if I can modify the fpga source code, I can run the examples in the application note.

   

Can you please comment on this?

   

thanks

   

rifo

[Anonymous]

we have tested with SP601. If the SP605 has the same harware connections/pinout and running at the same IO domain, then you can use it for this. For FX3 it doesn't matter, but you need to make sure that the volatage and timing requiremnets are met.

[ritu_2178811]

Hello,

   

I have asked this in xilinx forum and got the below answer. To summarize, all voltages on the FMC connector are set to 2.5V on SP605 and SP601

   

https://forums.xilinx.com/t5/Spartan-Family-FPGAs/Does-an-FMC-Card-designed-for-SP601-work-with-SP60...

   

Did you change the bank voltages on SP601, does default 2.5V is enough for fx3 superspeed kit?

   

thanks

   

rifo

[ritu_2178811]

Hello,

   

were you able to check whether 2.5V default bank voltage on FMC connectors are okey. I think that you didn't make any changes to the bank voltage settings on the FPGA ( that would have been told on the manual  )  but can you please still confirm it? 

   

Also if we change the voltage to 3.3V, so that parallel bus signals swing between 0 - 3.3V, wouldn't it better for reliability?

   

can you please help me in this regard

   

best regards

   

rifo

[ritu_2178811]

Hello,

   

I have checked the schematics of the super speed kit and indeed VIO_1 is being used as 3V3. I  believe that using the FPGA banks in 3V3 voltage level would be more robust. 

[agba_3844561]

Hi riforifo,

Have you succeeded on programming the SP605?

I am on the same venture now and I'm getting some issues.

Regards,

[agba_3844561]

Ok. As I said I tried doing it for SP605 and it worked!

I've uploaded the steps on how to do it on CYUSB3KIT-003_with_SP605_xilinx​ within the README.md file under the "Program FPGA" section.

Regards.