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I have a design that sends 8-bit data from an FPGA to the FX3. I have a manual DMA channel setup that has 4 buffers. When the application starts I can see from UART debug that it fills the 4 buffers but then it stops. The FLAGA goes low and no more data can be sent. Any idea why this is happening? Is it because the host isn't requesting this data so it just waits until it does? I am using the slave fifo code but I am using my own FPGA logic.
Thanks
Jon
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Yes, true!
If the host doesn't read the data, the FX3 buffers will get filled and no more data will be read. The host need to ask the data, thus freeing the buffers for next read.The flags indicate the availability of the buffers, in this case, it all got full. So, what you see on the flag, is an expected behavior: it is just indicating the master that it is not ready to take anymore data as the buffers are full. Please refer to AN65974, it describes in details the steps to test the slave-fifo functionality. Let us know for any further query!