Timer (UDB) and CPU in psoc 5lp

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song_285461
Level 3
Level 3
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How to Timer (UDB) and interrup on TC of (Timer) wokd  when CPU of Psoc 5lp not working?

   

Please tell me!

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AnkitaS_51
Employee
Employee
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The WDT circuit asserts a hardware reset to the device after a preprogrammed interval, unless it is periodically serviced in firmware.

   

The value of the reset status register (RESET_SR0) is read and cleared any time the device is booted.
That value is saved to a global SRAM variable.
 The watchdog reset (WRES) and software initiated reset (SRES) sources preserve the RESET_SR0 register. For more information,
refer to the device  TRM(page#142) available at these link-

   

http://www.cypress.com/file/123561/download

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HeLi_263931
Level 8
Level 8
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All logic in the UDB runs even with the CPU stopped. Think of it as having an additional logic curcuit in addition to the CPU.

   

When a timer creates in interrupt, it should wake up the CPU though, so it can handle the interrupt.

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Hello hli. I am using watch dog timer for reset CPU when it stop. I use 2 funtion:

   

set up  : CyWdtStart(CYWDT_1024_TICKS,CYWDT_LPMODE_NOCHANGE);// WATHDOG_TIME FOR RESET SYSTERM

   

end reset:CY_WDT_CR_REG = CY_WDT_CR_FEED; // reset watch dog

   

But I puted funtion :CY_WDT_CR_REG = CY_WDT_CR_FEED in a interrupt (10 ms) on TC of other timer:

   

CY(Timer)

   

{

   

CY_WDT_CR_REG = CY_WDT_CR_FEED;

   

}

   

Please Tell me: when CPU stop, watch dog timer do reset CPU or register of watch dog timer do reset?

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RTFM

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AnkitaS_51
Employee
Employee
100 likes received 50 likes received 25 likes received

The WDT circuit asserts a hardware reset to the device after a preprogrammed interval, unless it is periodically serviced in firmware.

   

The value of the reset status register (RESET_SR0) is read and cleared any time the device is booted.
That value is saved to a global SRAM variable.
 The watchdog reset (WRES) and software initiated reset (SRES) sources preserve the RESET_SR0 register. For more information,
refer to the device  TRM(page#142) available at these link-

   

http://www.cypress.com/file/123561/download

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