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Hi,
I need an 1ms Timer Interrupt, but I already use 8 TCPWM and 4 UDB for PWM ,so no more availible.
I only need a ISR every 1ms.
Regards,
Michael
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Please post your code so we can check it.
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... and one more suggestion: use the WDT (under low frequency clocks)
Bob
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WDT ist the best solution for me, but not easy to find...
Thanks Bob you are the greatest!
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Not too much!
Where in Germany are you located? I live near Bremen.
Bob
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I live near Osnabrück...
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I've found that if you have a little spare CPU time, you can implement several timers using the same hardware timer, and thus get more timers for the same hardware, but of course this adds more CPU usage, and multiplexes the timer between the software timers.
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As Bob mentioned, turning it into a component would involve malloc(), but since I'd rather not debug memory leaks, I've been working with the chip using compile-time operations. Here's a simple example showing the timer multiplexing; I don't have memory allocation like malloc in it, but I do have it scalable to the debug MAX_NUMBER_TIMERS, and it tells you if there is no more room for timers available.
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Thank you for demo. Very interesting solution utilizing single timer and isr at fixed rate.
For fast hardware timing (us scale), the Timer period can be updated to have only single isr call per "virtual timer". Below is an example of hardware-timed servo controls using single PWM module. The timing will become "hardware timed" as actual period update happens only on counter expiration.
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That's cool! Nice job on the hardware servo control 🙂
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Easiest is to use a callback function which is executed when the internal clock (you need to program one) equals a given value. Making that as universal as a component will require using malloc() and some linked list... Got some time ? ;-))
Bob
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Fortunately, when working with small numbers of timers, we can afford to skip linked lists in favor of a for loop 🙂