Verilog to C bidirectional data transfer

[Anonymous]

hi friends

   

I want to access a reg type variable in Verilog. Normally I can send data to verilog with CY_SET_REG8 command.

   

for example CY_SET_REG8(ParalelToSerial_1_MyTxReg__CONTROL_REG,0x81);

   

So How is the Verilog variable sent to the C side?

[odissey1 · Accepted solution]

Mucit23,

   

similar to http://www.cypress.com/comment/392376#comment-392376, reading is possible only from instantiated Control and Status registers using API function CY_GET_REG8(ParalelToSerial_1_MyTxReg__CONTROL_REG,0x81);

   

It is possible to read from control register only the value previously writtent to it by CY_SET_REG8(). To get back value from Verilog register "reg [7:0] myReg" you need instantiate a Status register, connect it to "myReg" and read from the status register using CY_GET_REG8.

[Anonymous]

Hi @odissey1

   

I have a problem in this regard. I wrote an SPI code in Verilog. 

   

    

`include "cypress.v"
//`#end` -- edit above this line, do not edit this line
// Generated on 04/07/2017 at 15:37
// Component: ParalelToSerial
module ParalelToSerial (
    output  Busy,
    output  Clkout,
    output  Dout,
    input   Clkin,
    input  [7:0] Din
);

    

//`#start body` -- edit after this line, do not edit this line

    

    reg dout;
    reg clkout;
    reg reset;
    reg tx_en;
    reg tx_start;
    reg tx_status;
    reg [7:0]tx_buf;
    reg [3:0]cnt_spi;

    

    cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
    TxStart(.control(tx_start));
    cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
    TxStatus(.control(tx_status));
    
    initial begin
      tx_start <= 1'b0;
      reset <= 1'b0;
      clkout <= 1'b0;
      tx_en <= 1'b0;
      cnt_spi <= 1'b0;
    end
    
    always @ (negedge Clkin)
    begin  
       if (tx_start == 1'b1 && reset == 1'b0)
       begin      
         reset <= 1'b1;
         tx_buf <= Din;
         tx_en <= 1'b1;
         tx_status <=1'b1;
       end
       
       if(tx_en == 1'b1)// shift işlemi yap
       begin    
            tx_buf <= {tx_buf[6:0], 1'b0};
            cnt_spi <= cnt_spi + 1; 
       end
       
       if(cnt_spi==7)  //aktarım tamamlandı
       begin
         cnt_spi <= 1'b0;
         tx_en <= 1'b0;
         tx_status <= 1'b0;
       end
    end

    

    assign Busy = tx_en;
    assign Dout = tx_buf[7];
    assign Clkout = tx_en & Clkin;    
    
//`#end` -- edit above this line, do not edit this line
endmodule

   

   

In the verilog code, I'm using the tx_status variable causes the compiler to fail. I can not use the tx_status variable with the cy_psoc3_control command.

   

The compiler gives the following error.

   

    

tx_status\'--Can't handle registered multi driver.

   

   

How can I solve this problem.?

[Anonymous]

Hi 

   

I have a problem with Verilog

   

The Always @ (*) block gives an error. Is usage in this way also valid on psoc?

[Bob_Marlowe]

There is a Warp Verilog Reference Guide already installed on your computer (Start -> Cypress -> Creator 4.0 -> Documentation....)

       

Bob