larger fifo for shift register

[Anonymous]

Hi,

   

i am trying to work with a 5Mbit/sec serial input and load it into a cyclic buffer i created in code. later in processing the data is sent over USB.
My problem is the FIFO depth. the code is just not fast enough to do something useful with the data and come back in time to prevent the  over flow. 

   

is there a way to chain fifo's ? would writing in verilog help ?

   

(i am using the CY8CKIT-059 PSOC5LP)

[Bob_Marlowe]

The two FIFOs are hardware and 4 entries deep and can be chained to form an 8 entry deep FIFO.

       

Bob

[odissey1]

Assaf,

   

it should be possible to utilize the ShiftReg component for buffering incoming data and off-loading it to RAM with DMA for further processing. I have no example of ShiftReg-DMA-RAM, but here are links to a similar task (RAM-DMA-ShiftReg). 

   

http://www.cypress.com/forum/psoc-5-device-programming/dma-shift-register

   

http://www.cypress.com/forum/psoc-5-device-programming/issues-dma-16bit-shiftreg

       

useful DMA links

   

http://www.cypress.com/documentation/application-notes/an52705-psoc-3-and-psoc-5lp-getting-started-d...

   

http://www.cypress.com/documentation/application-notes/an84810-psoc-3-and-psoc-5lp-advanced-dma-topi...

[Anonymous]

Thanks Bob,Odissey1 

   

Bob - could this be extended and chained to another UDB to add more depth? 

[Bob_Marlowe]

I am quite sure that FIFO cannot be extended in depth.

   

Using DMA as a double buffer could be a solution without (much) CPU overhead, Could be a pain in the a.. because Verilog is difficult to debug and DMA for PSoC5 tends to be complicated. But a rough estimation comes to > 3 MByte/s @ a 60MHz PSoC5 which would serve your requirements for speed easily. You even may use a second DMA channel for USB transmission.

       

Bob

[odissey1]

Assaf, as an alternative, it is easy to chain 8x 32-bit Shift Registers, producing 256-bit deep serial buffer (pic. shows only half). The drawback is that all UDBs will be spared. With DMA only one shift reg will be sufficient.