PSoC 5lp Simple SPI Design by Verilog?

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Anonymous
Not applicable

Hi

   

I am trying to build a simple SPI module with verilog.  I simply created a verilog module for this. I designed a block with clock input,  clock output and  data output.

   

My verilog codes are as follows.

   


`include "cypress.v"

module ParalelToSerial (
    output  CLKOUT,
    output  DOUT,
    input   CLKIN
);

   
    

//`#start body` -- edit after this line, do not edit this line
    reg clk_count;
    reg dout;
    reg clkout;    
    reg [7:0] status;
    reg [7:0] control_reg_out;
    
    cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
    MyTxReg(.control(control_reg_out));
    cy_psoc3_control #(.cy_init_value (8'b00000000), .cy_force_order(`TRUE)) //Default mode
    MyStatus(.control(status)); 
        
    always @ (posedge CLKIN)
    begin

    

       if(status==1'b1)
       begin
         clkout = 0;
         dout=control_reg_out[clk_count];
         clkout = 1;
         
         clk_count = clk_count + 1;
         
         if(clk_count == 😎
         begin
           status = 0;
           clk_count=0;
         end
       end
       else
       begin
          clk_count=0;
          dout=0;
          clkout=0;
       end
    end
       
    assign DOUT = dout;
    assign CLKOUT = clkout;
//`#end` -- edit above this line, do not edit this line
endmodule
//`#start footer` -- edit after this line, do not edit this line
//`#end` -- edit above this line, do not edit this lin

   
   

This codes not working. I must be making a mistake.

   

In main.c I send data to verilog with CY_SET_REG8 command.  

   

exactly as below

   

      CY_SET_REG8(ParalelToSerial_1_MyTxReg__CONTROL_REG,0x81); 
      CY_SET_REG8(ParalelToSerial_1_MyStatus__CONTROL_REG,0x01); 

   

What I would like to do is, if the status variable is 0x01, I want to send the 8 bit data in My TxReg as serial. It is very important for me to do this if I can do this I will increase the number of channels.

   

How can I solve this problem? Where do I make mistakes 

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1 Solution
odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted
        Mucit23, From first glance the verilog code above is unusable. You can find many code examples by googling "SPI verilog code".   

View solution in original post

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5 Replies
Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Will this

   

         clkout = 0;
         dout=control_reg_out[clk_count];
         clkout = 1;
work as you expect in verilog? Or will it generate a glitch pulse?

   

 

   

Bob

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Anonymous
Not applicable

Hi Bob

   

I am trying to make a very simple design. I have never used Verilog before. I need to generate a clock signal after data is transferred to the output.

   

I do not know how to do it. Verilog does not work as in C language. what should I do?

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

I'm not very fit in verilog. A generated pulse will need the provided clock. Set the output at the first LH transition and reset it at the next.

   

 

   

Bob

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Anonymous
Not applicable

Hi bob

   

I'm starting to solve the problem.Data output can be made. I just need to generate a clock signal. 

   

But I'm getting an error.

   

"fit.M0002:'\ParalelToSerial_1:status\'--Can't handle registered multi driver driver"

   

Why does this error result?

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted
        Mucit23, From first glance the verilog code above is unusable. You can find many code examples by googling "SPI verilog code".   
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