Switching currents stress PSOC GPIOs?

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CrVi_1101311
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Hello.
I recently made a design in which we have forgotten to put resistors to limit the current in the segments of a display (figure attached).

   

I have configured by SW the brightness (refresh rate 100hz ) and "seems" to work everything well. But I see that there are current peaks of 50mA(peak of 200ms) when the GPIO can not give that, (4mA as source ,41mA Max) and the Vout in the GPIO drops to 2,5V in this moment. I wonder if PSOC is suffering. Is it so?. PsoC has any type of current limitation to avoid this kind of problem?
Best regards.

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Welcome in the forum.

   

See the documentation of the I/O pin component. To maintain the logic level the maximum current is 4 to 20mA, the limitation for you will be the total IO current which is max 200mA. All "8" and a dot might be more than that.

   

 

   

Bob

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Bob_Marlowe
Level 10
Level 10
First like given 50 questions asked 10 questions asked

Welcome in the forum.

   

See the documentation of the I/O pin component. To maintain the logic level the maximum current is 4 to 20mA, the limitation for you will be the total IO current which is max 200mA. All "8" and a dot might be more than that.

   

 

   

Bob

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odissey1
Level 9
Level 9
First comment on KBA 1000 replies posted 750 replies posted

Crisanto, try setting output pins to "resistive pull up" or "resistive pull down" (depending on your configuration) to limit the current by using internal resistors (~5K).

CrVi_1101311
Level 3
Level 3
10 replies posted 5 replies posted 5 questions asked

Thanks for your reply.
As the chip did not heat I wondered was the real impact on the uC.
Perhaps this "bad behavior" is not significant in time.
With the pull-up is not seen practically :-(.
For security I will have to rebuild the PCB with Pull-UP resistors.
A greeting.

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