Anonymous
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Apr 20, 2017
02:23 AM
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Apr 20, 2017
02:23 AM
Dear All, my query is a liitel diffrent as follows:
1. Is there any uC from Cypress with on chip FPGA ..?
2. The UDB in PSOC uC has Sum-Of-Products & Macro-cell type architecture,which introduces delay. So, what the solution ?
3. Can we use UDB to implement any circuit which is written in Verilog, tested & simulated using Xillinx ?
4. can we force the MCU of PSOC uC to direct the instruction as such to the circuit in UDB & CPU of uC will be idle during that period.
thanks
Gulzar Singh
+91-9355828682
Solved! Go to Solution.
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PSoC 5LP
1 Solution
Apr 20, 2017
06:20 AM
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Apr 20, 2017
06:20 AM
1 Reply
Apr 20, 2017
06:20 AM
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Apr 20, 2017
06:20 AM
1, No 2, None 3, No 4, No