SImultaneous FIFO load/store

[PiWy_2406846]

Hello,

   

assume F0 is in dynamic, edge triggered mode and is controlled by UDB, (stores from A0). It contains [1, 2, 3, 4], A0=5. Now, let there be a datapath sequence of states

   

PASS A0, (A0 WR SRC = F0)

   

ADD A0, A0

   

and the FIFO write strobe generates a rising edge when control goes to the ADD. There are two possible scenarios in that state:

   

a) F0 = [2, 3, 4, 5], A0 = 1 (read and write were merged: I'd like this to happen)

   

or:

   

b) F0 = [2, 3, 4], A0 = 1 (because: A0 is first written to a full FIFO, so ignored, then the FIFO is read into A0)

   

or:

   

c) undefined.

   

Which one will happen? I can check it on a real device, but I don't consider it a proof of anything -- is there a documentation backup for that behavior?

   

    Best regards,

[GeonaP_26]

I think in either case it won’t matter, that 5 will be gone with your first instruction of passing A0 and loading A0 with F0. You need to store A0 somewhere on that cycle. If you set F0 input to ALU and load F0 on the first instruction then you would get the desired behavior.