ADC Single Sample mode funny behaviour

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Anonymous
Not applicable

Hi,

   

I am trying to work with Sigma-Delta ADC in single-sample mode for 16 bit in PSoC 5. I am testing my ADC by feeding it with 20Hz sine wave. This sine wave is generated by waveform DAC.

   

For 60 samples at sampling interval of 5 milli-sec about 6 peaks are expected from the ADC output [(60 *5ms)/50ms =6]. However I see 9 peaks when the raw ADC samples are plotted. I have attached the screenshot of the same.

   

Note :- I have checked the waveform DAC on the oscilloscope and 20Hz was observed.

   

Am I doing something wrong here ?

   

I am also attaching the project bundle.

   

My main.c looks something like this:

   

#define NO_SAMPLES 60
#define SAMPLING_INTERVAL_MS 5
#include <project.h>
#include<ADC_DelSig_1.h>

   

uint8 count=0;
int32 samples[NO_SAMPLES];

   

int main()
{
    
    CyGlobalIntEnable; /* Enable global interrupts. */
    WaveDAC8_1_Start();
    ADC_DelSig_1_Start();

   

    /* Place your initialization/startup code here (e.g. MyInst_Start()) */
    
    for(count =0; count<NO_SAMPLES;count++)
    {
        ADC_DelSig_1_StartConvert();
        if(ADC_DelSig_1_IsEndConversion(ADC_DelSig_1_WAIT_FOR_RESULT)!=0)
        {
            samples[count]=ADC_DelSig_1_GetResult32();
        }
        ADC_DelSig_1_StopConvert();
        CyDelay(SAMPLING_INTERVAL_MS);
    }   

   

}

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6 Replies
HeLi_263931
Level 8
Level 8
100 solutions authored 50 solutions authored 25 solutions authored

When you need exact timing, start your conversion based on a timer (via ISR). The way you are doing it now your delay is 5ms+time_for(conversion)+time_for(start_convert)+time_for(read_result)+time_for(stop_convert).

   

If you want to test this, toogle a pin with each _GetResult and maybe _StartConvert, and check their timing with the scope.

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Bob_Marlowe
Level 10
Level 10
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Your waveDAC frequency is 20kHz, your ADC sampling rate is only 200Hz (to be more precise about 150Hz). So what do you expect to see???

   

 

   

Bob

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HeLi_263931
Level 8
Level 8
100 solutions authored 50 solutions authored 25 solutions authored

"Aliasing" is the answer 🙂

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Anonymous
Not applicable

Wavedac frequency is 20Hz not 20Khz. So I do not think aliasing would be an issue here.My concern is why am I not getting 5ms(200Hz) as the sampling frequency? Why is there so much deviation ?

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Bob_Marlowe
Level 10
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Sorry, misread. It takes 2.18 ms after StartConvert() until a sample is ready, then you wait another 5 ms using CyDelay(). So there is no aliasing possible. When you want to measure in equal time slices I would suggest using a hardware trigger (timer) for the ADC soc signal and a high conversion rate (5 -10ksps). You even might use the eoc signal to trigger an interrupt that reads out the converted value (no waiting needed).

   

 

   

Bob

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Anonymous
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Thanks,

   

This time I tried by triggering the ADC's SOC by a counter, and getting samples in the ISR; interrupt triggered by ADC's EOC. 

   

This is very accurate. I am also attaching the ADC results.

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