3 Replies Latest reply on Jun 8, 2017 10:21 PM by XiGS_1880821

    Questions about AN61345 - EZ-USB FX2LP™ Slave FIFO Interface using FPGA


      Dear All,


          I refer to the design("AN61345 - Slave FIFO Interface using fpga"), and have been able to get the data, but this is not I want, the packet is too large; I hope to get a packet just 20 bytes, after to send 20 bytes data the fpga will output(PA6) a end packet signal to 68013, but I have modified the 68013 code, always can't succeed, so hope to get your help, thank you!


      GS Xie