the pin numbers are slightly misunderstood. If you look at the schematics of CYUSB3ACC-006, you will notice that the pins are divided in three blocks: J1A, J1B, J1C. All the block have 60 pins on the CYUSB3ACC board. But on the FPGA dev kit, you can notice that the part corresponding to J1A connection (J1 block 1) has only 40 pins. So the pin on block 2 of FPGA starts from pin 41 (in CYUSB3ACC it starts with 61). So, there is a mismatch. The pin 100 on CYUSB3ACC is getting connected to pin 80 of FPGA board's J1. Please let me know if you need any further clarification.
That's what I missed! Thank you!