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Hello,
I'd to know which is the best method in terms of speed to load a DMA from SRAM.
My DMA load 32 bit from SRAM and write this value into the Shift Register FIFO.
My instruction is:
CyDmaTdSetAddress(DMA_ShiftReg_TD[0], LO16((uint32)SSI_Tx.b), LO16((uint32)ShiftReg_interface_IN_FIFO_VAL_LSB_PTR));
where SSI_Tx is a union:
union {
uint32 l;
uint16 w[2];
uint8 b[4];
} SSI_Tx;
If I should change my instruction with the follow:
CyDmaTdSetAddress(DMA_ShiftReg_TD[0], LO16((uint32)fifo), LO16((uint32)ShiftReg_interface_IN_FIFO_VAL_LSB_PTR));
where "fifo" is an array:
uint32 fifo[4];
it would be more quicly to tranfer data from DMA to ShiftRegister or not?
Thanks and regards
Manuel
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PSoC 5LP
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Hello ,
Can you have a look at the section "Multi-Byte Data Alignment" in the document:"AN84810 - PSoC® 3 and PSoC 5LP Advanced DMA Topics". I hope that this will answer your queries.(Link:http://www.cypress.com/documentation/application-notes/an84810-psoc-3-and-psoc-5lp-advanced-dma-topi...).
Basically if the bytes are aligned, then the DMA transfer will be effective.
Thanks,
Hima
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please post your project
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Hello ,
Can you have a look at the section "Multi-Byte Data Alignment" in the document:"AN84810 - PSoC® 3 and PSoC 5LP Advanced DMA Topics". I hope that this will answer your queries.(Link:http://www.cypress.com/documentation/application-notes/an84810-psoc-3-and-psoc-5lp-advanced-dma-topi...).
Basically if the bytes are aligned, then the DMA transfer will be effective.
Thanks,
Hima