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Dear Sir/Madam
I am using CYF0018V33L high density FIFO.Input & output width is configured to 32 bits.Requirment is writing to FIFO and reading from fifo at 27MHz rate.Writing to the fifo is continuous and reading is done when 32k words are written.FPGA is used to write to and read from FIFO.Reading is done by generating RE signal when 32k words are written and fpga checks for DVAL signal to be low and value in the output data bus is latched to FPGA.But while analysing data its observerd that in every 32k-4 sample to 32k sample, same sample is repeated (4 cycles).4 words are missing in every set of 32k words.Pls suggest a way to get rid of this connundrum.
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Hello,
Is it happening in the same locations for every 32K sample size i.e always first four locations or last four locations are missing or is it random ?
Can you please us send us your code for review.
Thanks,
Krishna.
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Dear Sir/Madam
Thankyou for the prompt reply. Data missing in every 32k samples is in fixed fashion.4 words(each 32 bit) missing at the end of each 32k blocks. VHDL code for fifo interface is attached for your reference.In the code we are writing and reading incrementing pattern from 00 to FF.The data(binary format) which read through the checkout is also attached.Here data is missing in bytes (32k-15)86f1 to 86FF(32k-1) and this pattern is repeating after every 8700 bytes(32K).
We would be grateful if you could look into the matter as early as possible and solve the issue. This is urgently required to move ahead with our testing.
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Hi Akash,
We have contacted our product team regarding the issue. We will review the code ,debug and get back to you as soon as possible.
Thanks,
Krishna.