- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
All:
The attached project uses the SpiS component for TX only. The SpiClk is supplied from external input pin.
The SpiSS is controlled using a control register.
The block of data is just a buffer preloaed with data 0 thru 50.
The OScope screens show that it takes the SpiS 16 SpiCLk to tranfer each bit. Channel 1 is SpiClk, Ch3 is the data.
I am attaching only two screen shots (Xfer of 0x01 and then 0x03).
What am I doing wrong?
Appreciate any insight into this issue.
Giri
Solved! Go to Solution.
- Labels:
-
PSoC 5LP
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Please check if the SS is asserted before SCK. The scope shot does not look like the actual data you have pushed into the TX FIFO.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
Please check if the SS is asserted before SCK. The scope shot does not look like the actual data you have pushed into the TX FIFO.
- Mark as New
- Bookmark
- Subscribe
- Mute
- Subscribe to RSS Feed
- Permalink
- Report Inappropriate Content
That was the problem. Thanks.